Modern mobile devices such as smartphones make use of complex Systems-on-Chip (SoC) that often come with a DRAM chip stacked above the SoC. This packaging method that was designed to increase space efficiency is called a Package-on-Package (PoP). PoP has also an incidental impact on local Fault Injection methods such as Electromagnetic Fault Injection (EMFI). This paper shows that conventional EMFI may not always be the most effective approach for inducing faults into a SoC implemented in a PoP. We provide and compare methodologies to successfully induce faults within this kind of target. A PoP DRAM can be removed while keeping the SoC operationnal during the first boot stages. We applied this method and used conventional EMFI on a SoC without DRAM. We also present a new way to induce voltage glitches on the target power supply rail by using EM pulses. Conventional voltage glitches are also performed in order to compare the faults obtained. It appeared that faults injected by EM-induced glitches are closer to faults obtained with conventional EMFI than faults induced by conventional voltage glitches.

Integrated Circuits (ICs) have to be protected against threatening environmental radiations and malicious perturbations. A large panel of countermeasures has been developed to answer the needs of this challenging field. The Bulk Built-In Current Sensor (BBICS) is a highly reliable solution for the detection of these abnormal transient radiations that could induce a transient current in the Front-End of Line (FEoL). This paper proposes an innovative sensor based on the BBICS associated to the power-efficient emerging non-volatile memory Spin Transfer Torque Magnetic Random Access Memory (STTMRAM). The goal of this security solution is to detect both possible photoelectrical laser injections and thermal perturbations. Thus, the proposed architecture designated by Dual Detection of Heating and Photocurrent attacks (DDHP) highlights a dual detection efficiency, on the CMOS circuitry and on the Back-End of Line (BEoL) STT-MRAM technology.

Internet of Things (IoT) applications deployment relies on low-power circuits. Nowadays, on top of power consumption, security concern has become a real issue. Light-Weight Cryptography (LWC) has been developed to answer this challenge. In the lightweight cryptographic landscape, the PRESENT algorithm exhibits low power and small area features. At the same time, emergent resistive memory technologies such as Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) seem to be a strong candidate for Flash replacement with advanced design features such as hybridization with CMOS. In this context, we propose a hybrid CMOS/STT-MRAM technology for PRESENT cryptographic circuit for normally-off IoT applications. We demonstrate that the hybrid implementation is more power-efficient than the CMOS implementation when switched off for a period longer than 49.1 ms for a 180 nm CMOS core process with an area overhead of ×7. Based on this result, trends down to 28 nm node are studied and lead to outstanding performances with a power-effeciency of the hybrid version reached after 185 μs standby mode. In this scenario, an energy of 6,1 pJ is sufficient to store data in the Non-Volatile Flip-Flops (NVFFs) with a reduced area overhead of ×0.23.

The Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has been identified, by the International Technology Roadmap for Semiconductors (ITRS), as one of the most promising emerging technology. Different works handled the retention and reliability of STT-MRAM. However, to the best of our knowledge, the impact of a pulsed laser beam on STT-MRAM reliability and security has not been investigated so far as proposed in this paper. Since STT-MRAM are Back-end Of Line devices, we exposed the bit cells from the front-side to a 1064 nm wavelength laser pulse. The devices are electrically characterized (switching conditions between the two logical states) before and after the laser irradiation. The main result of this study is the demonstration of a resistance switching from Anti-Parallel (AP) to Parallel (P) state after the laser irradiation. That is how data integrity was altered by this irradiation, flipping the bit stored in this memory.