Current and future applications impose high demands on software-defined radio (SDR) platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous SDR MPSoC with a hexagonal network-on-chip to address these issues. It features four data processing modules and a baseband processing engine for iterative multiple-input multiple-output (MIMO) receiving. Integrated memory controllers enable dynamic data flow mapping and application isolation. In a 4 x 4 MIMO application scenario, the MPSoC achieves a throughput of 232 Mbit/s with a latency of 20 μs while consuming 414 mW. It outperforms state-of-the-art platforms in terms of throughput by a factor of 4.

This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction set extension tailored to fundamental data-intensive applications. We evaluate the MPSoC with typical database benchmarks focusing on scans and bitmap operations. When the processing elements operate on data stored in local memories, the chip consumes 250 mW and shows a 96x energy efficiency improvement compared to state-of-the-art platforms.

Turbo equalization has demonstrated to be a powerful approach for wireless transmission over frequency-selective channels introducing intersymbol interferences (ISI). Regarding multiple-input multiple-output (MIMO) systems, tree-search based MIMO detection techniques (e.g., sphere detection) are well suited for significantly reducing multi-antenna interferences. However, direct application of these detection techniques under the presence of ISI leads to vast processing complexity, increasing exponentially with the channel length and the number of transmitting antennas. In this paper, a low-complex two-stage approach is described splitting the interference reduction into a frequency-domain equalization stage and a time-domain sphere detection stage. Both are able to take a-priori information into account. Based on this, we derive a novel multi-iterative receiver, enabling powerful and adaptable processing with respect to the dominating interferences.

Single-carrier frequency-division multiplexing access (SC-FDMA) has been adopted as transmission scheme in Long Term Evolution (LTE) uplink to ensure low peak-to-average power ratio (PAPR). SC-FDMA inherently creates significant intersymbol interference (ISI), especially in large bandwidth scenarios. Additionally, inter-antenna interference (IAI) caused by transmitting spatially-multiplexed data streams in multiple-input multiple-output (MIMO) antenna systems further corrupts the received signal, making reliable estimation of the transmitted signal a computationally complex task. In this paper we propose an iterative receiver including a frequency-domain equalizer that mitigates both ISI and MAI jointly. The equalizer takes soft-input values in addition to the received SC-FDMA symbols into account to perform parallel interference cancellation (PIC). This soft-input is determined from decoders output values obtained in the previous receiving process, leading to equalization-decoding iterations. Simulation results for the LTE-Advanced uplink show that the proposed approach achieves considerable performance gains compared to non-iterative receivers.