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HuaXia Wang

dblp:125/1475 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › parasitic extraction
capacitance extraction		 0.212013
A Multilevel FFT Method for the 3-D Capacitance Extraction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Electronic design automation › physical design
parasitic extraction		 0.212013
A Multilevel FFT Method for the 3-D Capacitance Extraction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013

Methods — techniques the papers use, named apart from their topics

subdomain FFT · 0.2multilevel octree · 0.2multilevel interpolation/projection · 0.2multilevel fast fourier transform · 0.2
YearPublicationVenuePosition
2013 A Multilevel FFT Method for the 3-D Capacitance Extraction
abstract
We present a new multilevel fast Fourier transform (MLFFT) method and its application for the 3-D structures capacitance extraction. The multilevel octree structure, multilevel interpolation/projection, and subdomain FFTs techniques are employed in the MLFFT. Distinctions between the MLFFT and the conventional FFT-based methods are discussed carefully. Numerical results demonstrate that the MLFFT is more efficient than conventional FFT based methods, especially when analyzing inhomogeneous problems.
HuaXia Wang, Zhenhong Fan
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3