Demo Data from EDBT 2026 / reviewers in the wild / expert
Reef Eilers
dblp:125/2379
· DBLP profile ↗
4ranked-venue papers
1as first author
0since 2021 · last 2018
0000-0001-8964-4969ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-authorSoftware engineering, systems software and programming languages · 2Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Energy-efficient computing · 44% Integrated circuit design · 44% Hardware reliability and fault tolerance · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › low-power circuit design
leakage power estimation |
0.3 | 1 | 2018 | Leakage Models for High-Level Power Estimation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Energy-efficient computing
low-power design |
0.3 | 1 | 2018 | Leakage Models for High-Level Power Estimation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Hardware reliability and fault tolerance
process variation |
0.1 | 1 | 2018 | Leakage Models for High-Level Power Estimation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Methods — techniques the papers use, named apart from their topics
monte carlo simulation · 0.3BSIM compact model · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Leakage Models for High-Level Power EstimationabstractLeakage currents are one major concern when designing recent CMOS devices, making design for leakage at all stages of the design process mandatory. Early leakage optimization requires early leakage prediction, and for electronic system level design, this means estimation capabilities at register transfer (RT) level or above. Existing models are very accurate, but slow [transistor level such as Berkeley Simulator (BSIM)], or the slightly faster gate level models (such as the Liberty library), disregard relevant parameters. We present RT level leakage macro models, which are faster than recent gate level models, while preserving the accuracy of the transistor level models to a great extent. An estimation framework is proposed, describing the subthreshold, gate, and junction leakage of recent technology devices. The models are characterized using BSIM compact models and a Monte Carlo process variation description. Each varying BSIM parameter can be described. As an example of use, channel length, oxide thickness, and channel doping are regarded together with the temperature, supply voltage and body voltage. The final macro model needs less than a hundred parameters to capture the leakage behavior of an entire RT component and is still analytically describing the dependence to the process parameters. Compared to SPICE + BSIM, a model prediction is computed up to a hundred times faster for large RT components, and is, depending on the analyzed technology, within 2.1% (for 16-nm LP)-6.8% (for 65-nm bulk) deviation over a wide range of operating conditions and process variation settings. Domenik Helms, Reef Eilers, Malte Metzdorf, Wolfgang Nebel |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2016 | RT level timing modeling for aging prediction
Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel |
DATE | 3 |
| 2016 | Analysis of NBTI effects on high frequency digital circuits
Ahmet Unutulmaz, Domenik Helms, Reef Eilers, Malte Metzdorf, Ben Kaczer, Wolfgang Nebel |
DATE | 3 |
| 2014 | Efficient NBTI modeling technique considering recovery effectsabstractThe aging effect "Negative Bias Temperature Instability", which is highly dependent on device history, has a direct impact on the design of integrated circuits. In order to make realistic predictions available in the design process, simulation durations of existing history aware models must be significantly reduced. Therefore, a performance-oriented, yet accurate abstraction of the switching trap NBTI model is presented within this paper. Evaluation results for various stress scenarios demonstrate very precise NBTI simulations and a major improvement to another performance-oriented model abstraction. Simulation durations facilitate realistic aging predictions of larger components in a reasonable period of time. Reef Eilers, Malte Metzdorf, Domenik Helms, Wolfgang Nebel |
ISLPED | 1 |