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T. W. Copley

dblp:125/2394 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 38% Interconnection networks and networks-on-chip · 38% Embedded and real-time systems · 12%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › network topology
reconfigurable topology		 0.011989
A high performance reconfigurable parallel processing architecture · SC 1989
Embedded and real-time systems
DSP applications		 0.011989
A high performance reconfigurable parallel processing architecture · SC 1989
Hardware reliability and fault tolerance › network fault tolerance
fault-tolerant network reconfiguration		 0.011989
A high performance reconfigurable parallel processing architecture · SC 1989

Methods — techniques the papers use, named apart from their topics

3-d multichip packaging · 0.0
YearPublicationVenuePosition
1989 A high performance reconfigurable parallel processing architecture
abstract
The architecture of the AT&T DSP-3 parallel processor is described. The DSP-3 design is modular and when implemented with 128 processing nodes, provides a maximum throughput of 3.2 GFLOPS (32 bit floating point). The high speed interconnection network (40 Mbytes/sec) contains redundant paths that allow the machine to be configured in a variety of topologies. This flexibility supports efficient operation for a diverse set of signal processing applications and enables topology reconfiguration in support of fault tolerance. Advanced multi-chip 3-D packaging will allow a 800 MFLOP version of the machine to be realized in a multi-processor array volume of 9 cubic inches.
Richard R. Shively, E. B. Morgan, T. W. Copley, Allen L. Gorin
 SC3