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Jun Kohdate

dblp:125/2403 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 61% Electronic design automation · 30% Performance modeling and evaluation · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
dataflow computing
0.011989
A preceding activation scheme with graph unfolding for the parallel processing system-array · SC 1989
Electronic design automation › high-level synthesis › scheduling
dataflow graph scheduling
0.011989
A preceding activation scheme with graph unfolding for the parallel processing system-array · SC 1989
Parallel and multicore computing
parallel program transformation
0.011989
A preceding activation scheme with graph unfolding for the parallel processing system-array · SC 1989
Performance modeling and evaluation › simulation
simulation-based evaluation
0.011989
A preceding activation scheme with graph unfolding for the parallel processing system-array · SC 1989

Methods — techniques the papers use, named apart from their topics

graph unfolding · 0.0dataflow graph construction · 0.0
YearPublicationVenuePosition
1989 A preceding activation scheme with graph unfolding for the parallel processing system-array
abstract
The purpose of this paper is to propose and evaluate a new scheme, called the Preceding Activation Scheme with Graph Unfolding, which translates a FORTRAN program into a dataflow graph and executes it efficiently. The problems in restructuring a FORTRAN program into a dataflow graph are that (1) a FORTRAN program is not written in a single assignment rule and (2) it has an explicit control flow. These problems result in little parallelism because many gate-operations, such as T/F gates, are introduced in the dataflow graph to synchronize the data movement. Therefore, discarding these gate-operations is the key to exposing parallelism in a FORTRAN program. In this paper, the preceding activation scheme with graph unfolding is proposed to discard these gate-operations. Then, the result of the performance evaluation by the -Harray- software simulator is presented. It is shown that the execution speed with the proposed scheme for flow graphs without backward branches is about 1.5 times as fast as that with the extended activation scheme which initiates the execution only after it is confirmed that a basic block will be selected at a conditional branch. Moreover, the execution speed is 2.7 times as fast as that with the extended activation scheme if a flow graph including backward branches are unfolded by the proposed scheme.
Hayato Yamana, Takashi Hagiwara, Jun Kohdate, Yoichi Muraoka
SC3