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James H. Pomerene

dblp:125/5034 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1956
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 53% Integrated circuit design · 47%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › arithmetic unit
arithmetic logic unit		 0.011955
Fast Carry Logic for Digital Computers · IRE Trans. Electron. Comput. 1955
Integrated circuit design
digital circuit design		 0.011956
A Note on High-Speed Digital Multiplication · IRE Trans. Electron. Comput. 1956
Processor architecture and microarchitecture › computer arithmetic
binary addition		 0.011955
Fast Carry Logic for Digital Computers · IRE Trans. Electron. Comput. 1955
YearPublicationVenuePosition
1956 A Note on High-Speed Digital Multiplication
Gerald Estrin, Bruce Gilchrist, James H. Pomerene
 IRE Trans. Electron. Comput.3
1955 Fast Carry Logic for Digital Computers
abstract
Existing large scale binary computers typically must allow for the maximum full length carry time in each addition. It has been shown that average carry sequences are significantly shorter than this maximum, on the average only five stages for a 40 digit addition. A method is described to realize the implied 8 to 1 time saving by deriving an actual ``carry completion'' signal. Experimental results verify this saving.
Bruce Gilchrist, James H. Pomerene, S. Y. Wong
 IRE Trans. Electron. Comput.2