In this work, a wireless power and data transmission system (WPDT) for fully implantable cochlear implants that operates with a broad range of input power is implemented. In this inductive link, power conversion efficiency is maximized by switching the operation modes of the multi-mode rectifier according to the power sourcing capability under varying coupling conditions. These operation modes are named as half wave mode (HWM) and voltage mode (VM). While the input power of the transmitter is generated with a Class-E power amplifier, data transmission is conducted with differential binary phase shift keying. A large gain common gate amplifier is utilized to compensate variable input signal level. Data and carrier recovery is realized by an asymmetric charge-discharge structure with threshold detection. This novel WPDT circuit is implemented and fabricated in TSMC 180 nm BCD Technology with an active area of 1.2 mm2. Average charging power values of the system for a 3.3 V load are measured as 42.96 mW, 38.90 mW, and 60.10 mW for only HWM, only VM, and mixed mode rectification for a transmitted power range of 10 - 140 mW. Meanwhile, BPSK demodulator consumes only 22.8 - 24.1 μW power and has a bit error rate (BER) range of 3.0x 10-3 - 2.8 x 10-6 depending on receiver coil voltage level (50 - 300 mV).

Power consumption in neural stimulation devices such as cochlear implants, or retinal implants, is an important issue. These devices operate in volume constrained conditions and therefore have a drawback in terms of energy storage. This means that the converters used for the necessary voltage compliance in these devices must be as efficient as possible. This work describes a system implementing an adaptive converter together with a constant current stimulator. The adaptive converter utilizes a three-stage charge pump with a total of 600 pF on-chip MIM capacitors occupying 1 mm2area. Fed from a single supply, it can provide 3.3/6/9/12 V output with varying load current between 100 to 900 μA. The converter changes its output, i.e., stimulator supply voltage depending on the digitally controlled stimulation current. This eliminates the unused voltage headroom and provides more efficient operation compared to constant voltage converters. In addition, reduced number of bulky off-chip flying capacitors make the converter appealing for volume constricted stimulators, such as fully implantable cochlear implants. An H-bridge was used to create the stimulation current, enabling single supply operation. Operational stage number and pulse frequency modulation was utilized to configure the output. In-vitro tests show a decrease of up to 79% in the power dissipation of the constant current stimulator compared to its constant 12 V operation.

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design.

Charge balancing is a major concern in functional electrical stimulation. Any excess charge accumulation over time leads to electrolysis with the electrode dissolution and tissue destruction. Therefore, charge balance circuits are used for mitigating the effects of charge accumulation in tissues. This work introduces an active synchronous charge balance circuit for constant current neural stimulators that operates without requiring negative supply for remaining charge detection. The charge balance circuit detects the residual charge by monitoring the electrode voltages just before the stimulation. If the voltage difference between the electrodes is above a certain threshold, a balance current is generated to achieve net zero charge at the electrode. Balancing current and the main stimulation current are injected simultaneously, preventing any interference in other electrodes. The charge balance circuit is dynamically disabled to reduce the system power when the charge detection is not active. The circuit can operate for the stimulation currents up to 1.4 mA and hold the electrode charge under 8 nC/phase while consuming only 6.36 μW power.

The fully implantable cochlear implant (FICI) interface circuit proposed in this work senses sound harmonics from 8 different piezoelectric cantilever sensors, and generates pulse width modulated biphasic current outputs to stimulate the auditory neurons. Signals from the piezoelectric sensors are amplified, rectified, and sampled. The sampled voltage is held and converted to current by a novel logarithmic voltage-to-current converter. The current is then digitized with a current comparator to determine the width of the generated biphasic current pulses. Continuous interleaved sampling (CIS) is used as the stimulation technique for 8 channels operation. The system is designed and implemented in 0.18 μm HV CMOS process. Measurements show that the circuit is able to generate 15 to 62.5 μs biphasic current pulses with 400 μA peak amplitude, as the input range varies from 60 dB to 105 dB sound pressure level. The total power consumption of 82 and 513 μW have been measured at 70 dB input for 1-channel and have been extrapolated for 8-channels configurations, respectively, which are the lowest powers for FICI interface electronics to the best of our knowledge.

This paper presents an ultralow power interface circuit for a fully implantable cochlear implant (FICI) system that stimulates the auditory nerves inside cochlea. The input sound is detected with a multifrequency piezoelectric (PZT) sensor array, is signal-processed through a front-end circuit module, and is delivered to the nerves through current stimulation in proportion to the sound level. The front-end unit reduces the power dissipation by combining amplification and compression of the sensor output through an ultralow power logarithmic amplifier. The amplified signal is envelope detected, and fed to a voltage-controlled current source as a reference for stimulation current generation. The single channel performance has been tested with a thin film pulsed-laser deposition (PLD) PZT sensor for sound levels between 60- and 100-dB sound pressure level (SPL). The proposed front-end signal conditioning unit, which can support different back-end stimulators, dissipates only 25.4 and 51.2 μW based on measurement, for 1- and 8-channel operation, respectively. This represents the lowest in the literature. The interface generates linear stimulation current of 110-430 μA for the given sound range. The single-channel and eight-channel stimulator consume 105 and 691 μW, respectively, for 110-μA biphasic stimulation current.

This paper presents research at The University of Michigan on micromachined capacitive silicon accelerometers and gyroscopes with their interface electronics to satisfy the requirements for inertial navigation applications. The accelerometer systems developed employ in-plane (lateral), out-of-plane (z-axis), and single-chip 3-axis sensors with the interface electronics. The interface electronics forms a second-order electromechanical sigma-delta modulator together with the sensor and the system can be operated in both open and closed-loop. These devices can achieve better than 2 /spl mu/g//spl radic/Hz resolution with a range of /spl plusmn/1.35 g. The single-crystal silicon ring gyroscope provides 132 mV/deg/sec sensitivity and 10 deg/hour resolution.