Anandarup Das

dblp:125/7108 · DBLP profile ↗
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5ranked-venue papers
0as first author
3since 2021 · last 2025
0000-0001-5326-9570ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 3 since 2021
YearPublicationVenuePosition
2025 A Capacitor-Coupled SEPIC and Ćuk based Successive Folding Inverter for PV Systems
abstract
Unfolder type converters present some attractive features for grid-connected systems, such as switching loss and filter size reduction, inherent common-mode noise suppression, immunity to cable reflection, etc. However, most of the commonly used unfolder topologies in high power applications have discontinuous input current. Additionally, isolation is usually achieved through high frequency transformers. A new capacitor-isolated single-stage converter with continuous input current is presented in this paper. The capacitive isolation increases converter power density, improves efficiency due to removal of core losses, and reduces converter weight. Additionally, rather than unfolding, the proposed converter makes use of a new concept being named ’successive folding’. The converter circuit reduces to a positive or negative gain type converter based on the output half cycle. In each half cycle, the converter operates with a variable duty ratio to produce the desired sinusoidal output. A SEPIC and Ćuk based circuit is selected owing to continuous input current and topological similarities. The converter operating principle, design and control is highlighted. Simulation results are presented to verify the operation.
Abhrodip Chaudhury, Anandarup Das
IECON2
2023 A Three Port Three-Phase Modular Series Multilevel Converter Integrating MVDC with MVAC Grids
abstract
Multiport Modular Multilevel Converters (MMCs) are gaining importance for future hybrid MVDC, MVAC grid integration. This paper proposes a three-port three phase Modular Series Multilevel Converter (MSMC) integrating medium voltage direct current (MVDC) with different frequency (50Hz and 60Hz) medium voltage alternate current (MVAC) grids simultaneously using passive filters. The proposed topology has reduced number of arms (three arms per AC grid) and reduced semiconductor device count compared to conventional three phase MMC. Further the proposed topology preserves all the features of conventional half bridge (HB) sub-modules (SMs) based MMC such as scalability, modularity etc. The operation, equivalent circuit during steady state and design of passive filters are discussed in detail. The working proposed converter is verified in control hardware-in-loop (OPAL-RT) platform.
Sukrashis Sarkar, Subhasis Nayak, Anandarup Das
IECON3
2021 Fault Limiting Circuit based protection for DC and AC Faults in HB-MMC HVDC Systems
abstract
The Half bridge Modular Multilevel Converter (HB-MMC) based High Voltage Direct Current (HVDC) Transmission systems faces various challenges due to DC faults and AC faults. In case of DC faults (pole-to-pole and pole-to-ground fault), the high fault current flowing through MMC arms may damage the devices present in the MMC. Among the AC faults, the valve side single phase to ground (SPG) fault in HB-MMC based asymmetrical monopolar and bipolar HVDC system is one of the most serious faults. It produces some special characteristics like non-zero crossing of the grid side currents which prevent the AC Circuit breakers (ACCBs) present in the grid side from operating; further, capacitor overvoltage happens in upper arm submodules. In this paper, a Fault Limiting Circuit (FLC) is proposed to solve the above problems. The proposed circuit acts as a parallel LC resonant circuit formed by inserting a capacitor in parallel to arm inductor during fault condition which provides high impedance to the fault current path and reduces the fault current. This circuit is activated during fault condition only, hence the efficiency of the converter is not compromised. The operation of the FLC with HB-MMC is analyzed and verified by simulation in EMTP platform, showing a good agreement between simulation results and theoretical analysis.
Sukrashis Sarkar, Anandarup Das
IECON2
2019 An Isolated DC-DC MMC for HVDC Tapping
abstract
This paper proposes an isolated DC-DC MMC topology with a wide range of voltage conversion ratio meant for High Voltage DC tapping operation. The proposed converter topology operates with two stages of power conversion i.e. DC/AC/DC with an intermediate medium frequency transformer. The MMC is connected to the high voltage DC side and acts as an inverter. The output of the MMC is connected to the primary side of transformer. The secondary of the transformer at medium voltage level is connected to a Voltage Source Converter (VSC) and acts as a rectifier. The frequency of the intermediate AC stage has been chosen around 500 Hz. A passive series LC filter helps in circulating the AC current in the primary side of the converter. Increase in the intermediate AC frequency will reduce the size of the transformer and other passive elements significantly in the circuit. Sinusoidal level shifted PWM technique is implemented in the proposed converter which creates a multistep AC output across the transformer reducing the stress at the transformer terminal. The theoretical analysis is validated by simulation and experimental results.
Nibedita Parida, Anandarup Das
IECON2
2019 A Novel Zero Sequence Voltage Injection for Extending Active Power Balancing in Grid tied Solar PV Powered Cascaded H-Bridge Converter
abstract
Cascaded H-bridge converter is a promising candidate for large scale grid connected solar PV plant. However, non-uniform power among the phases of the converter occurs due to non-uniform irradiation and temperature of the cells. This causes unbalanced grid currents which is not acceptable according to the standard grid codes. A fundamental zero sequence voltage is therefore injected to balance the grid currents. But, high degree of unbalance in power generation among the phases leads to over modulation in the cells. This can happen during failure of PV modules. To avoid the over modulation, a novel zero sequence voltage is proposed in this paper. It increases the power balancing capability of the converter. The zero sequence voltage injection is implemented through a novel PWM clamping method. For obtaining the novel zero sequence voltage, a control scheme is also presented. The proposed technique is verified through simulation in MATLAB Simulink and through experiment in the lab prototype.
Rahul Sharma 0012, Anandarup Das
IECON2