Demo Data from EDBT 2026 / reviewers in the wild / expert
Juan Carlos Juega
dblp:125/7608
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › code generation
GPU code generation |
0.2 | 1 | 2013 | Polyhedral parallel code generation for CUDA · ACM Trans. Archit. Code Optim. 2013 |
Compilers and program optimization
parallelizing compiler |
0.2 | 1 | 2013 | Polyhedral parallel code generation for CUDA · ACM Trans. Archit. Code Optim. 2013 |
GPUs and heterogeneous computing
GPU computing |
0.2 | 1 | 2013 | Polyhedral parallel code generation for CUDA · ACM Trans. Archit. Code Optim. 2013 |
Methods — techniques the papers use, named apart from their topics
polyhedral compilation · 0.3multilevel tiling · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | Adaptive Mapping and Parameter Selection Scheme to Improve Automatic Code Generation for GPUs
Juan Carlos Juega, José Ignacio Gómez, Christian Tenllado, Francky Catthoor |
CGO | 1 |
| 2013 | Polyhedral parallel code generation for CUDAabstractThis article addresses the compilation of a sequential program for parallel execution on a modern GPU. To this end, we present a novel source-to-source compiler called PPCG. PPCG singles out for its ability to accelerate computations from any static control loop nest, generating multiple CUDA kernels when necessary. We introduce a multilevel tiling strategy and a code generation scheme for the parallelization and locality optimization of imperfectly nested loops, managing memory and exposing concurrency according to the constraints of modern GPUs. We evaluate our algorithms and tool on the entire PolyBench suite. Sven Verdoolaege, Juan Carlos Juega, Albert Cohen 0001, José Ignacio Gómez, Christian Tenllado, Francky Catthoor |
ACM Trans. Archit. Code Optim. | 2 |