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Jimmy Cleary

dblp:125/7642 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 77% Processor architecture and microarchitecture · 23%
Software engineering, system software, and programming languages
1 paper
Concurrent programming · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Concurrent programming › synchronization
synchronization primitives
0.212013
Fast asymmetric thread synchronization · ACM Trans. Archit. Code Optim. 2013
Parallel and multicore computing › synchronization
thread synchronization
0.212013
Fast asymmetric thread synchronization · ACM Trans. Archit. Code Optim. 2013
Processor architecture and microarchitecture
chip multiprocessor
0.012013
Fast asymmetric thread synchronization · ACM Trans. Archit. Code Optim. 2013

Methods — techniques the papers use, named apart from their topics

message passing · 0.3biased locks · 0.3
YearPublicationVenuePosition
2013 Fast asymmetric thread synchronization
abstract
For most multi-threaded applications, data structures must be shared between threads. Ensuring thread safety on these data structures incurs overhead in the form of locking and other synchronization mechanisms. Where data is shared among multiple threads these costs are unavoidable. However, a common access pattern is that data is accessed primarily by one dominant thread, and only very rarely by the other, non-dominant threads. Previous research has proposed biased locks, which are optimized for a single dominant thread, at the cost of greater overheads for non-dominant threads. In this article we propose a new family of biased synchronization mechanisms that, using a modified interface, push accesses to shared data from the non-dominant threads to the dominant one, via a novel set of message passing mechanisms. We present mechanisms for protecting critical sections, for queueing work, for caching shared data in registers where it is safe to do so, and for asynchronous critical section accesses. We present results for the conventional Intel® Sandy Bridge processor and for the emerging network-optimized many-core IBM® PowerEN™ processor. We find that our algorithms compete well with existing biased locking algorithms, and, in particular, perform better than existing algorithms as accesses from non-dominant threads increase.
Jimmy Cleary, Owen Callanan, Mark Purcell, David Gregg
ACM Trans. Archit. Code Optim.1