In three-level neutral-point clamped (NPC) converters, carrier-based techniques are widely applied to solve the inherent capacitor voltage balancing problem as well as the common-mode voltage (CMV) mitigation. This article proposes a novel approach to simultaneously address the voltage balancing and CMV issues in a three-phase three-level single-end inverter. It can reduce the dv/dt actions (33%-66%) as well as restricting the CMV magnitude to one-sixth of DC voltage while eliminating the low-frequency voltage oscillation at the dc-ink neutral point. The proposed control method cohesively combines two methods (Method I and Method II) and selects them according to the neutral point (NP) voltage balancing condition. Method I generates four dv/dt actions in a switching cycle with higher voltage balancing ability while Method II only generates two dv/dt actions in a switching cycle with lower voltage balancing ability. Experiments are performed to validate the proposed control method. Additionally, this work observes and investigates the non-ideal phenomenon in practical circuits that causes spikes in the CMV that should have been eliminated from the modulation point of view, which have not been well studied in the literature where explanations and solutions are provided.

While the conventional methods are based on sinusoidal excitations to parameterize the loss of magnetic components, recent studies have justified the characterization directly through large-signal, rectangular excitations, as are experienced in typical power electronics converters. The Triple Pulse Test (TPT) has been proposed previously for this purpose as a discontinuous procedure to characterize the high-frequency loss of magnetics. The excitation circuit used to deliver the TPT is advanced in this paper by removing the need for two external power supplies. Instead, a single power supply is connected to a voltage-offsetting input stage which uses a novel implementation of a half-bridge circuit to deliver a controllable offset between two capacitor banks. This dc-link offsetting circuit can compensate the asymmetric voltage drops on the power devices and delivers rectangular voltages with symmetric amplitude to form closed BH loops on the device under test. The aim is for the integrated testbed is to deliver the TPT autonomously, iterating over several operating points, to generate a loss map of one magnetic component. This testbed could subsequently aid the manufacturer of magnetics to shift from material-based datasheet to component-based, which will enable the end users to model high-frequency magnetics more easily and accurately.

This paper comprehensively utilizes three control freedoms, i.e., switching state selection, zero sequence injection(ZSI) and redundant level modulation(RLM), to maintain capacitor voltage balance in two five-level three-phase converters over the full range of modulation index and power factor. The calculation process of the proposed control method is explained in detail. This method is easy to implement and can be used in other multilevel converters. The first topology is proposed for the first time in this paper. The capacitor voltage controllable region of the second topology has been extended to full operation range without extra circuits. Voltage jumps are found during the deadtime. The performance of the proposed topology and control method is verified by simulation and experiment.

Power loss modelling of magnetic components becomes increasingly important in the design of modern power electronic converters, especially in the case of higher switching frequencies enabled by emerging wide-bandgap devices. While the modelling of the active power electronic devices is relatively mature and straightforward, the estimation of the passive magnetic component loss remains challenging, including both the core loss and winding (copper) loss. As indicated by recent studies, the accurate prediction of the core loss in power converters relies on rectangular-voltage-excited measurements. To characterize the core loss with high-frequency rectangular excitations and dc-biases, a Triple Pulse Test (TPT) has been proposed and is further extended in this paper. The TPT involves a discontinuous procedure and a bidirectional, half-bridge excitation circuit that supplies transitional high rectangular voltage and high current. The importance and practical considerations of achieving closed dynamic BH loops are discussed. The proposed TPT is analogous to the common Double Pulse Test (DPT) for power electronics devices in terms of the testing circuit, the measurement instruments, and the discontinuous procedure. Moreover, the winding loss characterization can also be achieved by the TPT, given the winding loss can be very difficult to predict especially for randomly wound components where analytical equations cannot be applied accurately. Eventually, a complete loss dataset for one magnetic component design (i.e. same core material, shape and winding arrangement) can be built from TPT, which can be utilized to accurately model the inductor loss in power converter applications.

A four-level π-type converter is a Neutral Point Clamped (NPC) multilevel converter topology for low/medium voltage applications. As the inherent issue with this topology, the DC-link capacitor voltage balancing is challenging, especially when it operates as a single-end inverter/rectifier with unity power factor. This paper proposes a closed-loop DC-link voltage balancing algorithm of a π-type converter that is effective and simple to implement. In principle, this approach is based on Redundant Level Modulation (RLM). The RLM utilizes additional voltage levels in each switching window to gain extra controllability of the DC-link capacitor voltages without affecting the average output voltage. An algorithm based on mathematical and logical operations is developed to utilize RLM to achieve the closed-loop voltage balancing. The proposed control method is effective over the full modulation index ( M=0 ~ 1.15) and full power factor range (cosφ = 0 ~ 1). The algorithm is implemented in a test rig, and the experiment confirms its effectiveness.