Graph neural networks for Hardware Trojan detection are typically evaluated on fully observed gate-level netlists, whereas practical settings often provide only partial observations due to reverse engineering limitations, extraction loss, and obfuscation. This makes robustness evaluation inherently challenging. We present NetLossBench, the first tiered robustness benchmark for budgeted stress testing under observation-layer information loss. NetLossBench defines three tiers of loss generation: random loss as a baseline, structured loss guided by topology-aware heuristics to approximate realistic observation loss, and adversarial loss guided by reinforcement learning to approximate worst-case degradation. Results show that random loss can overestimate robustness, while structured and adversarial losses reveal a lower robustness floor.

Electronic Design Automation (EDA) plays a crucial role in classical chip design and significantly influences the development of quantum chip design. However, traditional EDA tools cannot be directly applied to quantum chip design due to vast differences compared to the classical realm. Several EDA products tailored for quantum chip design currently exist, yet they only cover partial stages of the quantum chip design process instead of offering a fully comprehensive solution. Additionally, they often encounter issues such as limited automation, steep learning curves, challenges in integrating with actual fabrication processes, and difficulties in expanding functionality. To address these issues, we developed a full-stack EDA tool specifically for quantum chip design, called EDA-Q. The design workflow incorporates functionalities present in existing quantum EDA tools while supplementing critical design stages such as device mapping and fabrication process mapping, which users expect. EDA-Q utilizes a unique architecture to achieve exceptional scalability and flexibility. The integrated design mode guarantees algorithm compatibility with different chip components, while employing a specialized interactive processing mode to offer users a straightforward and adaptable command interface. Application examples demonstrate that EDA-Q significantly reduces chip design cycles, enhances automation levels, and decreases the time required for manual intervention. Multiple rounds of testing on the designed chip have validated the effectiveness of EDA-Q in practical applications.

Traditional edge accelerators struggle to balance performance, accuracy, and power consumption. Our solution leverages Asynchronous Stream Computing (ASC) to implement a fully asynchronous, clockless system where data is encoded in the frequency and duty cycle of streams. This architecture adapts dynamically to available energy resources, adjusting computational precision and speed in response to workload demands. A stimulus-driven model allows the system to process data efficiently when actionable information is present. Analytical and experimental results highlight a tunable trade-off between latency and precision, aligning system performance with real-time requirements. To validate these concepts, we implement a Compute-in-Memory (CiM) based dot product architecture to accelerate Word2Vec Algorithms for Natural Language Processing (NLP) tasks and have exhibited a relative semantic accuracy scaling of 47.81% and a computational efficiency scaling of 43.23x when scaling precision from 12 - 4 bits.

Using radio frequency (RF) energy to power Internet of Things (IoT) devices over extended distances poses a challenge due to limited input power. As we move farther from the source, the intensity of radio waves diminishes according to an inverse square law. Implementing an internal feedback body biasing connection using flipped-well transistors can dynamically enhance the rectifier’s conductivity and eliminate the need for external circuitry. In this work, we propose a novel feedback self-adaptive body biasing rectifier for RF energy harvesting for the UHF band (902-928 MHz). Based on 22nm fully-depleted silicon-on-insulator (FDSOI) technology, this rectifier achieves the high sensitivity required to harvest weak signals at far distances and a competitive power conversion efficiency (PCE). Furthermore, we introduce a methodology for designing and optimizing a differential impedance matching network (IMN) and rectifier. Based on the simulation results, our proposed 5-stage rectifier exhibits a high sensitivity of -31.4dBm at 1V under a capacitive load, surpassing comparable results achieved by previous works. A good peak PCE of 31.3% under a 5MΩ load at the typical corner makes our rectifier an ideal choice for ultra-low power RF energy harvesting applications.

Layer-wise mixed-precision quantization (MPQ) has become prevailing for edge inference since it strikes a better balance between accuracy and efficiency compared to the uniform quantization scheme. Existing MPQ strategies either lacked hardware awareness or incurred huge computation costs, which gated their deployment at the edge. In this work, we propose a novel MPQ search algorithm that obtains an optimal scheme by "sampling" layer-wise sensitivity with respect to a newly proposed metric that incorporates both accuracy and proxy of hardware cost. To further efficiently deploy post-training MPQ on edge chips, we propose to tightly integrate the quantized inference units as part of the processor pipeline through micro-architecture and Instruction Set Architecture (ISA) co-design. Evaluation results show that the proposed search algorithm achieves 3% ~ 11% higher inference accuracy with similar hardware cost compared to the state-of-the-art MPQ strategies. In addition, the tightly integrated MPQ units achieve speedup of 15.13x ~ 29.65x compared to a baseline RISC-V processor.

Electric traction is one of the most promising technologies that can lead to significant improvements in vehicle performance, energy utilization efficiency, and polluting emissions. Among several technologies, hybrid electric vehicle (HEV) traction is the most promising technology that has the advantages of high performance, high fuel efficiency, low emissions, and long operating range. Moreover, the technologies of all the component hardware are technically and markedly available. At present, almost all the major automotive manufacturers are developing hybrid electric vehicles, and some of them have marketed their productions, such as Toyota and Honda. This paper reviews the present technologies of HEVs in the range of drivetrain configuration, electric motor drives, and energy storages