Shun-Ren Siao

dblp:126/1752 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 83% Integrated circuit design · 17%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › layout density control
dummy fill insertion
0.212013
1-D Cell Generation With Printability Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Electronic design automation › physical design
layout optimization
0.212013
1-D Cell Generation With Printability Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Electronic design automation
physical design
0.212013
1-D Cell Generation With Printability Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Integrated circuit design
digital circuit design
0.012013
1-D Cell Generation With Printability Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Integrated circuit design › ASIC design
standard cell design
0.012013
1-D Cell Generation With Printability Enhancement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013

Methods — techniques the papers use, named apart from their topics

line-end gap optimization · 0.2
YearPublicationVenuePosition
2013 1-D Cell Generation With Printability Enhancement
abstract
As process technologies advance to the subwavelength era, the 1-D design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. To improve the printability of 1-D cell design, it is essential to insert dummy patterns and optimize line-end gap distribution for each layer. This paper presents novel 1-D cell generation algorithms that simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, minimize used routing tracks, insert sufficient dummy patterns, and eliminate stage-like line-end gaps without power and timing overhead. Consequently, the 1-D cell area is minimized and the printability of the cell is enhanced. To the best of our knowledge, this is also the first work in the literature that considers line-end gap distribution during 1-D cell generation.
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.6