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Mrinal Deo

dblp:126/2054 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
GPUs and heterogeneous computing · 100%
Theoretical computer science
1 paper
Algorithms and data structures · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing › GPU computing
GPU algorithms
0.212013
Parallel suffix array and least common prefix for the GPU · PPoPP 2013
Algorithms and data structures › sequence algorithms
string algorithms
0.212013
Parallel suffix array and least common prefix for the GPU · PPoPP 2013
GPUs and heterogeneous computing › GPU computing
GPU implementation
0.012013
Parallel suffix array and least common prefix for the GPU · PPoPP 2013

Methods — techniques the papers use, named apart from their topics

skew algorithm · 0.3induced copying · 0.3OpenCL · 0.3
YearPublicationVenuePosition
2013 Parallel suffix array and least common prefix for the GPU
abstract
Suffix Array (SA) is a data structure formed by sorting the suffixes of a string into lexicographic order. SAs have been used in a variety of applications, most notably in pattern matching and Burrows-Wheeler Transform (BWT) based lossless data compression. SAs have also become the data structure of choice for many, if not all, string processing problems to which suffix tree methodology is applicable. Over the last two decades researchers have proposed many suffix array construction algorithm (SACAs). We do a systematic study of the main classes of SACAs with the intent of mapping them onto a data parallel architecture like the GPU. We conclude that skew algorithm [12], a linear time recursive algorithm, is the best candidate for GPUs as all its phases can be efficiently mapped to a data parallel hardware. Our OpenCL implementation of skew algorithm achieves a throughput of up to 25 MStrings/sec and a speedup of up to 34x and 5.8x over a single threaded CPU implementation using a discrete GPU and APU respectively. We also compare our OpenCL implementation against the fastest known CPU implementation based on induced copying and achieve a speedup of up to 3.7x. Using SA we construct BWT on GPU and achieve a speedup of 11x over the fastest known BWT on GPU.
Mrinal Deo, Sean Keely
PPoPP1