Petr Musil

dblp:126/3440 · DBLP profile ↗
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5ranked-venue papers
2as first author
1since 2021 · last 2021
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Reconfigurable computing and FPGAs · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › vision accelerator
object detection accelerator
0.212013
High performance architecture for object detection in streamed video (abstract only) · FPGA 2013
Reconfigurable computing and FPGAs
FPGA implementation
0.012013
High performance architecture for object detection in streamed video (abstract only) · FPGA 2013

Methods — techniques the papers use, named apart from their topics

waldboost · 0.2scanning window classifier · 0.2
YearPublicationVenuePosition
2021 Unconstrained License Plate Detection in Hardware
Petr Musil, Roman Juránek, Pavel Zemcík
VEHITS1
2020 Cascaded Stripe Memory Engines for Multi-Scale Object Detection in FPGA
abstract
Object detection in embedded systems is important for many contemporary applications that involve vision and scene analysis. In this paper, we propose a novel architecture for object detection implemented in FPGA, based on the Stripe Memory Engine (SME), and point out shortcomings of existing architectures. SME processes a stream of image data so that it stores a narrow stripe of the input image and its scaled versions and uses a detector unit which is efficiently pipelined across multiple image positions within the SME. We show how to process images with up to 4K resolution at high frame rates using cascades of SMEs. As a detector algorithm, the SMEs use boosted soft cascade with simple image features that require only pixel comparisons and look-up tables; therefore, they are well suitable for hardware implemenation. We describe the components of our architecture and compare it to several published works in several configurations. As an example, we implemented face detection and license plate detection applications that work with HD images (1280 ×720 pixels) running at over 60 frames/s on Xilinx Zynq platform. We analyzed their power consumption, evaluated the accuracy of our detectors, and compared them to Haar Cascades from OpenCV that are often used by other authors. We show that our detectors offer better accuracy as well as performance at lower power consumption.
Petr Musil, Roman Juránek, Martin Musil, Pavel Zemcík
IEEE Trans. Circuits Syst. Video Technol.1
2013 High performance architecture for object detection in streamed video (abstract only)
abstract
Object detection is one of the key tasks in computer vision. It is computationally intensive and it is reasonable to accelerate it in hardware. The possible benefits of the acceleration are reduction of the computational load of the host computer system, increase of the overall performance of the applications, and reduction of the power consumption. We present novel architecture for multi-scale object detection in video streams. The architecture uses scanning window classifiers produced by WaldBoost learning algorithm, and simple image features. It employs small image buffer for data under processing, and on-the-fly scaling units to enable detection of object in multiple scales. The whole processing chain is pipelined and thus more image windows are processed in parallel. We implemented the engine in Spartan 6 FPGA and we show that it can process 640x480 pixel video streams at over 160 frames per second without the need of external memory. The design takes only a fraction of resources, compared to similar state of the art approaches.
Pavel Zemcík, Roman Juránek, Petr Musil, Martin Musil, Michal Hradis
FPGA3
2013 High performance architecture for object detection in streamed videos
abstract
In this paper, we introduce a novel architecture of an engine for high performance multi-scale detection of objects in videos based on WaldBoost training algorithm. The key properties of the architecture include processing of streamed data and low resource consumption. We implemented the engine in FPGA and we show that it can process 640×480 pixel video streams at over 160 fps without the need of external memory. We evaluate the design on the face detection task, compare it to state of the art designs, and discuss its features and limitations.
Pavel Zemcík, Roman Juránek, Petr Musil, Martin Musil, Michal Hradis
FPL3
2013 High performance FPGA object detector: Hardware prototype
abstract
Summary form only given. In this demo, we introduce a novel architecture of an engine for high performance multi-scale detection of objects in videos based on WaldBoost training algorithm. The key properties of the architecture include processing of streamed data and low resource consumption. We implemented the engine in FPGA and we show that it can process 640 × 480 pixel video streams at over 160 FPS without the need of external memory.
Pavel Zemcík, Roman Juránek, Petr Musil, Martin Musil, Michal Hradis
FPL3