Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Ingeol Lee

dblp:126/5522 · DBLP profile ↗
← Back
2ranked-venue papers
1as first author
0since 2021 · last 2020
0000-0002-3156-6512ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 75% Integrated circuit design · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
3d integration
0.412020
A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Hardware reliability and fault tolerance
fault-tolerant architecture
0.412020
A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Hardware reliability and fault tolerance › redundancy
TSV redundancy
0.412020
A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Hardware reliability and fault tolerance › defect tolerance
TSV repair
0.412020
A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020

Methods — techniques the papers use, named apart from their topics

cube-based face replacement · 0.4
YearPublicationVenuePosition
2020 A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults
abstract
Three-dimensional integrated circuits (3-D ICs), which feature many benefits, such as high bandwidth and a high degree of integration, have recently received considerable attention from the semiconductor industry. However, these chips feature through-silicon vias (TSVs), which vertically connect multiple dies, and these TSVs may fail, resulting in a decreased yield. Unfortunately, previously proposed methods to repair TSVs cannot handle certain failure patterns. For example, existing techniques cannot repair clustered TSV faults, which commonly occur in practice. Furthermore, the number of signal TSVs typically determines the number of redundant TSVs, which may result in wasteful and redundant TSVs. In this paper, a new TSV repair scheme is proposed that replaces defective TSVs with redundant TSVs by utilizing the architecture of a cube, which can replace any face with any of the other faces. Both signal TSVs and redundant TSVs are placed in the face of cube, so any faulted TSVs can be replaced with redundant TSVs. The experimental results indicate that the new method guarantees 100% coverage with any number of signal TSVs and redundant TSVs.
Minho Cheong, Ingeol Lee, Sungho Kang 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2019 Highly Reliable Redundant TSV Architecture for Clustered Faults
abstract
A three-dimensional (3-D) integration technology involving the use of a through-silicon-via (TSV) offers advantages such as low power consumption, small form factor, and large bandwidth. However, owing to the incompleteness of the 3-D manufacturing process, TSVs may exhibit some inherent defects; hence, switching and shifting repairing methods have been proposed. These methods repair the TSV faults by rerouting the signals of the faulty TSVs to the other signal TSVs or redundant TSVs using a simple repair algorithm. However, if one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the FTSV increases, i.e., the TSV defects tend to be clustered. Therefore, recently proposed repair solutions, such as ring/router-based repair architectures, have focused on clustered TSV faults. However, the implementation of these existing repair solutions for clustered faults involves an extremely high hardware overhead. This study proposes a TSV redundancy architecture to repair clustered TSV faults with a high repair rate and low hardware overhead. The proposed architecture divides the TSVs into several groups and connects the TSVs of each group using a 2:1 multiplexer chain. Simulation results show that the proposed architecture exhibits a repair rate of 98.52% for uniformly distributed faults and 69.86% for highly clustered faults. These repair rates are higher than those of other TSV redundancy architectures and the difference in the repair rate becomes even greater if the faults are more clustered. Moreover, the approach yields a 58.55% reduced area as compared to that of the router-based redundancy architecture, which also targets the repair of clustered faults.
Ingeol Lee, Minho Cheong, Sungho Kang 0001
IEEE Trans. Reliab.1