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He Yi

dblp:126/7435 · DBLP profile ↗
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7ranked-venue papers
2as first author
0since 2021 · last 2020
0000-0003-0799-2471ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5Applied, interdisciplinary, general and emerging computing · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.422015
Layout optimization and template pattern verification for directed self-assembly (DSA) · DAC 2015
Directed Self-Assembly (DSA) Template Pattern Verification · DAC 2014
Electronic design automation
physical design
0.422015
Layout optimization and template pattern verification for directed self-assembly (DSA) · DAC 2015
Directed Self-Assembly (DSA) Template Pattern Verification · DAC 2014
Electronic design automation › physical design
layout optimization
0.212015
Layout optimization and template pattern verification for directed self-assembly (DSA) · DAC 2015
Electronic design automation › physical design
layout verification
0.212015
Layout optimization and template pattern verification for directed self-assembly (DSA) · DAC 2015
Electronic design automation › physical design › lithography
lithography hotspot detection
0.212014
Directed Self-Assembly (DSA) Template Pattern Verification · DAC 2014
Electronic design automation › physical design
lithography
0.112014
Directed Self-Assembly (DSA) Template Pattern Verification · DAC 2014

Methods — techniques the papers use, named apart from their topics

directed self-assembly · 0.2block copolymer lithography · 0.2segment distance features · 0.2point correspondence · 0.2machine learning · 0.2
YearPublicationVenuePosition
2020 Reliabilities of Some Multistate Consecutive-k Systems
abstract
In this paper, we consider four different kinds of multistate consecutive-k systems, namely a multistate linear m-consecutive-k-out-of-n: G system, a multistate linear consecutive-k-out-of-n: G system with sparse d, a multistate linear m-consecutive-k-out-of-n: G system with sparse d, and a multistate linear: G system. The reliability formulas for these systems are derived by using the finite Markov chain imbedding approach. Unlike some previous research, the vectors m, k, d, and f do not need to be monotonic in this paper. Some illustrative examples are also presented to show how the reliabilities of the four multistate consecutive-k systems are calculated.
He Yi, Lirong Cui, Hongda Gao
IEEE Trans. Reliab.1
2018 Multipoint and Multi-Interval Covering Availabilities
abstract
In the field of reliability, there are many indexes, such as reliability, point availability, interval availability, and others, which have been widely used to describe the properties of repairable systems. However, some situations of interest cannot be covered by the existing indexes. In this paper, we introduce the definitions of multipoint covering availability and multi-interval covering availability, and formulas are derived in matrix forms for aggregated Markov repairable systems especially when the covering working intervals can overlap. The formulas of binary-point and binary-interval covering availabilities are given by an enumeration method. For multipoint and multi-interval problems, a recursive method is employed. Numerical examples are shown to illustrate the results derived in this paper and finally some conclusions and discussions are presented.
He Yi, Lirong Cui, Jingyuan Shen
IEEE Trans. Reliab.1
2015 Contact pitch and location prediction for Directed Self-Assembly template verification
abstract
Directed Self-Assembly (DSA) is a promising technique for contacts/vias patterning in 7 nm technology nodes. In DSA process, groups of contact holes/vias are generated by the self-assembly process guided by the `guiding templates'. The guiding templates are patterned by conventional optical lithography process such as 193 nm immersion lithography. As a result, the patterning fidelity and variation in the template shapes is very likely to affect the final contact holes/vias. While feasible in principle, rigorous DSA process simulation is unacceptably slow for full chip verification in practice. This paper proposes a machine learning based verification that can predict the pitch size of the contact holes and the hole centers. Given a set of training data that consists of simulated template and contact hole patterns, our method is able to learn a highly accurate predictive model for pitch size and hole location. To build a statistical model for prediction, we utilize computer vision techniques to extract various geometric and image features. We conduct extensive experiments to explore the effectiveness of the proposed features, and compare several machine learning algorithms to achieve an effective and efficient prediction. The experimental results show that compared to the minutes or even hours of simulation time in rigorous methods, our best prediction model achieves very promising results (RMSE = 0.135 pitch grid) with less than one second of training and predicting runtime overhead.
Zigang Xiao, Yuelin Du, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang 0001
ASP-DAC4
2015 Layout optimization and template pattern verification for directed self-assembly (DSA)
abstract
Recently, block copolymer directed self-assembly (DSA) has demonstrated great advantages in patterning contacts/vias for the 7 nm technology node and beyond. The high throughput and low process cost of DSA makes it the most promising candidate in patterning tight pitched dense patterns for the next generation lithography. Since DSA is very sensitive to the shapes and distributions of the guiding templates, it is necessary to develop new EDA algorithms and tools to address the patterning rules and constraints of the process. This paper presents a set of DSA-aware optimization techniques targeting the most urgent problems for DSA technology, including layout optimization and template pattern verification.
Zigang Xiao, Daifeng Guo, Martin D. F. Wong, He Yi, Maryann C. Tung, H.-S. Philip Wong
DAC4
2015 Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning
abstract
The continued scaling of feature size has brought increasingly significant challenges to conventional optical lithography.[1-3] The rising cost and limited resolution of current lithography technologies have opened up opportunities for alternative patterning approaches. Among the emerging patterning approaches, block copolymer self-assembly for device fabrication has been envisioned for over a decade. Block copolymer DSA is a result of spontaneous microphase separation of block copolymer films, forming periodic microdomains including cylinders, spheres, and lamellae, in the same way that snowflakes and clamshells are formed in nature - by self-assembly due to forces of nature (Fig. 1a). DSA can generate closely packed and well controlled sub-20 nm features with low cost and high throughput, therefore stands out among other emerging lithographic solutions, including extreme ultraviolet lithography (EUV), electron beam lithography (e-beam), and multiple patterning lithography (MPL).[2;6]
H.-S. Philip Wong, He Yi, Maryann C. Tung, Kye Okabe
ISPD2
2014 Directed Self-Assembly (DSA) Template Pattern Verification
abstract
Directed Self-Assembly (DSA) is a promising technique for contacts/vias patterning, where groups of contacts/vias are patterned by guiding templates. As the templates are patterned by traditional lithography, their shapes may vary due to the process variations, which will ultimately affect the contacts/vias even for the same type of template. Due to the complexity of the DSA process, rigorous process simulation is unacceptably slow for full chip verification. This paper formulate several critical problems in DSA verification, and proposes a design automation methodology that consists of a data preparation and a model learning stage. We present a novel DSA model with Point Correspondence and Segment Distance features for robust learning. Following the methodology, we propose an effective machine learning (ML) based method for DSA hotspot detection. The results of our initial experiments have already demonstrated the high-efficiency of our ML-based approach with over 85% detection accuracy. Compared to the minutes or even hours of simulation time in rigorous method, the methodology in this paper validates the research potential along this direction.
Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang 0001
DAC5
2013 Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library
abstract
At the 10 nm technology node, the contact layers of integrated circuits (IC) designs are too dense to be printed by single exposure using 193 nm immersion (193i) lithography. Among all the emerging patterning approaches, block copolymer directed self-assembly (DSA) is a promising candidate with high throughput and low cost for sub-20 nm features. Traditionally, the study of DSA has focused on achieving periodic regular patterns over large area. Realizing that long range order is not needed for patterning irregularly distributed contact holes, we use topographical guiding templates to alter the natural symmetry of block copolymer and achieve controlled irregular DSA patterns. However, DSA patterning must satisfy the overlay accuracy requirements while the guiding templates also need to be printable by conventional lithography. This presents a unique opportunity of DSA patterning and layout design co-optimization for improving the manufacturability of DSA. This paper discusses the DSA-aware contact layer optimization problem for 10 nm 1D standard cell library. For the first time we propose a cost function for each DSA template based on its overlay accuracy performance. Then given a standard cell library, we simultaneously optimize the layouts of every cell, such that the contact layer of any cell in the library can be fully patterned by a set of guiding templates, and the total cost of the templates is minimal. This optimization problem is first proved to be NP-hard and formulated as a Weighted Partial Maximum Satisfiability (MAXSAT) problem, which can be optimally solved with a public SAT solver. Then we propose a bounded approximation algorithm that solves the problem much more efficiently. The experimental results demonstrate that our approach is remarkably promising in practice and validate the proposed optimization problem.
Yuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang 0001, Qiang Ma 0002
ICCAD4