We propose switching activity factor-based effective current source model (SAFE) for aging-aware static timing analysis (STA), a new technique for estimating the timing performance of digital circuits. SAFE is based on the development of device-level variation-aware analytical timing models of stacked and multistage logic cells (commonly employed transistor topologies in a synthesized netlist of a random logic path), which drastically reduces the recharacterization efforts of the standard cells. The models developed are derived as a function of input transition time$(T_{R})$and load capacitance$(C_{L})$. The timing performance of a standard cell degrades with threshold voltage$(V_{\mathrm {th}})$degradation in a MOS device due to various aging mechanisms. SAFE, makes the entire STA process aging aware by updating its model coefficients with$V_{\mathrm {th}}$degradation caused by aging. It is achieved by proposing a method for estimating$V_{\mathrm {th}}$degradation under various stress conditions, including static, dynamic, and asymmetric, that applies to any process design kit (PDK). To consider asymmetric aging, we have developed a method to find effective switching activity factor$(\alpha _{\mathrm {eff}})$for N-stage stacked and N-stage parallel logic which is used to find the value of switching activity factor$(\alpha)$at intermediate nodes in pipelined logic circuits. Our simulations are performed in Mentor Graphics Eldo SPICE environment using STMicroelectronics 28 and 65-nm CMOS process. The proposed technique provides a high-simulation accuracy (2.5% average error) when compared with SPICE simulations. Finally, we achieved a ~98.14% reduction in the required number of simulations using SAFE when compared with a completely SPICE/Aging simulation-based approach.

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage$(V_{\mathrm{ th}})$of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ($t$). A device-level approach for$V_{\mathrm{ th}}$degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of$t$. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with$t$to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations.

In this article, a variation-aware design methodology for high-performance MOS-varactor voltage-controlled ring oscillator (MV-VCRO) in near-threshold-voltage (NTV) regime is proposed. The MV-VCRO is suitable because it eliminates series-stack transistors and generates rail-to-rail swing. For the first time, delay-models for conventional, bulk-driven (BD), and dynamic-threshold (DT) MV-VCROs considering nonlinearity in NTV regime is presented using effective drive current ( Ieff) and MOS-varactor capacitance models. The proposed design methodology is intuitive and considers process-voltage-temperature (PVT) variations at an initial stage of the design for width-length optimization. The methodology is highly efficient and does not require performing time-consuming Monte-Carlo (MC) simulations at post-layout stages. Look-up tables (LUTs) for MOS-varactor average-capacitances, and Ieffare generated while considering the regions of device operation during MV-VCRO output-node transitions while extracting the model parameters from one-time simulations. This approach is physics/topology-based and is verified in HSPICE and Sentaurus 2-D-TCAD simulations using STM65nm and 32 nm, respectively. The Ieff-models predict the oscillation frequency ( fOSC) with an accuracy of 97%, 96%, 97% for conventional, BD, DT-MV-VCRO, respectively. Furthermore, our estimated LUT- Ieff-capacitance models account for the change in fOSC, tuning range, and voltage-controlled oscillator (VCO)-gain with PVT variations with an accuracy-efficiency of 96%-99% compared to MC simulations. Furthermore, using LUTs, phase-noise, power consumption, and layout-area optimization technique is presented for a particular fOSC. Finally, the design methodology ensures that the desired fOSCis within the “linear” range of the VCO's-gain due to statistical variation of Vth, VDD, etc. This ensures resilience to PVT variations for NTV-VCO in linear feedback systems.