This article presents a 28/39 GHz dual-band multi-mode low-noise amplifier (LNA), supporting wideband, concurrent, and reconfigurable dual-band operation modes. The proposed LNA consists of a three-stage cascode amplifier topology. The first and second stage loads incorporate a multi-tap switchable inductor and a reconfigurable transformer-based dual-band network, respectively. The primary coil inductance of the switchable inductor can be tuned by controlling the voltage of the secondary coil switches. The proposed reconfigurable dual-band network, comprising a transformer-based high-orderLCnetwork, provides different frequency responses for wideband, concurrent and reconfigurable modes. To mitigate the losses introduced by the transformer and switch, a Colpitts-style negative resistance compensation network (NRCN) is utilized. Fabricated in a 40-nm CMOS process, the LNA achieves the following measured performance: in wideband mode, the peak gain is 19.6 dB with a 3-dB bandwidth of 24.5-42.9 GHz, 3.4 dB minimum noise figure (NF), -9.6 to -6.5 dBm output 1-dB compression point (OP1dB). In concurrent mode, the measured results show the peak gains of 24/23.2 dB, 3.2/3.6 dB minimum NF and -11.8 to -7.6/-6.9 to -5.5 dBm OP1dB with 3-dB bandwidths of 25-31.7/38.1-42.5 GHz. The measured peak gains are 23.5/22dB with 3.1/3.5 dB minimum NF, -8.4 to -6.9/-7.3 to -4.9 dBm OP1dB and 3-dB bandwidths of 25.6-33.8/35.3-43.5 GHz in reconfigurable mode. The LNA occupies a core area of 0.14 mm2and consumes 15.2 mW, 19 mW, and 15.2 mW in wideband, concurrent, and reconfigurable modes, respectively.

A high-speed multimodulus divider (MMD) is proposed in a 65-nm CMOS process. A 7-bit programmable counter (PC) featuring an innovative end-of-count (EOC) architecture and high-speed reset configuration is proposed for MMD applications. The proposed PC achieves an operating frequency of 11.7 GHz, which is 64.8% higher than the previously reported state-of-the-art design. In addition, an innovative analogous digital-standard-cell (A-STD) layout methodology is introduced to optimize parasitic capacitance and chip area in MMD implementation. By utilizing the above techniques along with a 20.5 GHz high-speed true-single-phase-clock (TSPC) dual-modulus prescaler (DMP), the MMD achieves a division-ratio range from 40 to 323, with a maximum frequency of 12.6 GHz at 1.2-V supply, consuming a total power of 3.07 mW. And by using the A-STD layout methodology, the MMD occupies a small chip area. The chip area of MMD is$56 \times 36 {\,}\boldsymbol {\mu }\text {m}^{2}$, which is less than 20% of that of prior works with similar functionality.

The task of moving magnetic target localization involves recovering hidden states from noisy, nonlinear magnetic field observations. While nonlinear filters like the extended Kalman filter (EKF) and unscented Kalman filter (UKF) are effective, they depend heavily on knowledge of underlying noise statistics. Besides, a lack of prior knowledge can lead to poor accuracy and robustness in state estimation. To address these two limitations, this paper proposes a novel filtering algorithm that automatically estimates the initial state value. An initial value estimator is created using three-axis magnetic scalar gradient data and the Euler deconvolution to quickly determine the target’s initial state. This value is then used as prior knowledge in a new neural network-aided Kalman filter called KalmanNet for state prediction and updating. Unlike traditional methods that transform nonlinear equations into linear forms, the proposed method does not require specific assumptions, preserving target characterization generality. Furthermore, this method provides a reliable initial state value while not rely on statistical noise knowledge, enhancing estimation accuracy. Simulation and field experiment show that the estimation results closely align with true values. In field experiment, the RMSE values for position, velocity, and magnetic moment vectors were reduced by 69.21%, 86.30%, and 60.55% compared to the EKF, and by 75.49%, 83.74%, and 80.45% compared to the UKF.

This paper proposes a millimeter-wave (mmW) oscillator with “$2+1$” cores and triple operation modes to realize an octave-tuning range. An auxiliary core, comprising a switch and a negative transconductance cell, is introduced to the regular dual-core oscillator to generate a third mode with enhanced effective Q. This auxiliary core not only broadens the tuning range without compromising phase noise or chip area but also avoids the risk of introducing mismatch into two regular cores like triple-core oscillators. The demand for low interconnect resistance is relieved because of the merits of less core mismatch and extra magnetic injection lock path. The behavior of the proposed oscillator in different modes is studied analytically. A quantitative analysis of phase noise and interconnect resistance in the dual-core oscillator is presented and verified against circuit simulations. Implemented in a 65-nm CMOS process, the oscillator achieves a 72.24% tuning range from 16.35 to 35.48 GHz and a peak figure-of-merit of tuning range and area (FoM$_{\mathrm {TA}}$) of -217.07 dBc/Hz at 20.27 GHz with 1 MHz frequency offset. The chip operates from a 1 V supply with a power consumption from 6.3 to 21.76 mW and a core area of 0.075 mm2.

This paper presents a 6-bit bidirectional variable-gain vector-summing active phase shifter (BVG-AVSPS) in TSMC 65nm CMOS technology. The proposed BVG-AVSPS consists of a novel bidirectional quadrature generator, four dual-function bidirectional amplifiers and two input/output matching networks. The proposed hybrid-based quadrature generator achieves low orthogonal amplitude and phase mismatches over a wideband with bidirectionality. Dual-function bidirectional amplifiers are employed to achieve either vector modulation or gain control functions in different operational directions. To improve the phase shifting accuracy during gain tuning, compensation transistors are employed in the dual-function bidirectional amplifiers to minimize additional phase variation. The proposed input/output networks based on L-type coupled inductors ensure proper impedance matching for both input and output in TX and RX modes. For both TX and RX modes over 24 GHz~32 GHz, the measured RMS phase and gain errors are 1.25∘~2.4∘and 0.42 dB~0.56 dB throughout 12.3 dB gain tuning range, respectively. With the help of the compensation transistors, measured phase variation is less than ±2.1∘during output gain tuning. The core area of proposed BVG-AVSPS is 625 µm×355 µm.