This brief presents a double-data-rate (DDR) ripple counter with calibration circuits for correlated multiple sampling (CMS) in CMOS image sensors (CISs). This brief analyzes a specific type of least significant bit (LSB) error that obstructs the recording of the prior LSB count result during continuous counting processes when performing digital correlated double sampling (DDS) and digital CMS. This error stems from the transparent characteristic of the LSB in DDR counter and causes the increase of random noise. A calibration circuit is presented to calibrate the LSB error, which achieves carry propagation and retains the remainder by recording the result of the LSB after each quantization. The random noise is reduced by 25.5% based on simulation results in different CMS iterations after calibration. A$1280\times 1024$prototype CIS is fabricated in a 110-nm 1P4M process. The experimental results show that at DDS mode, the CIS random noise is$147~\mu \text { V}_{\text {rms}}$and ADC power consumption is$21.07~\mu $W, whereas at CMS =2, the noise is$118~\mu \text { V}_{\text {rms}}$and power consumption is$28.07~\mu $W. In addition, the prototype CIS has a column FPN of 0.006%.

We describe a method of optical flow extraction for high-speed high-brightness targets based on a pulse array image sensor (PAIS). PAIS is a retina-like image sensor with pixels triggered by light; it can convert light into a series of pulse intervals. This method can obtain optical flow from pulse data directly by accumulating continuous pulses. The triggered points can be used to filter redundant data when the target is brighter than the background. The method takes full advantage of the rapid response of PAIS to high-brightness targets. We applied this method to extract the optical flow of high-speed turntables with different background brightness, with the sensor model and actual data, respectively. Under the sampling condition of 2×10 4 frames/s, the optical flow could be extracted from a high-speed turntable rotating at 1000 r/min. More than 90% of redundant points could be filtered by our method. Experimental results showed that the optical flow extraction algorithm based on pulse data can extract the optical flow information of high-brightness objects efficiently without the need to reconstruct images.

Abstract This paper proposed a high‐speed target tracking algorithm based on the pulse‐sequence‐based image sensor. The algorithm separates the target from the background through the statistical distribution of the pulses in a single frame of data. In order to achieve more accurate target tracking, the phenomenon of image lag in the process of capturing the high‐speed moving target is studied. The positioning deviation is compensated by estimating the image lag length of the moving target. The algorithm is implemented with pipeline processing on field‐programmable gate array (FPGA). The positioning accuracy of the algorithm is verified with input data from a pulse‐sequence image sensor model. The verification results show that the maximum position deviation of the target at different speeds is 0.94 pixels. In the experiment of tracking a 40 m/s moving ball, this algorithm can provide real‐time position information within 44 ns.

Active image sensors can only record scenes at low frame rates. The dynamic vision sensor (DVS) can capture high-speed scenes under challenging lighting conditions. However, DVS discards absolute light intensity information. The dynamic and active pixel vision image sensor (DAVIS) can output events and low-frame-rate grayscale images simultaneously. This paper proposes a high frame rate video reconstruction and deblurring algorithm based on events and low-speed blurred image sequences from DAVIS. First, we visualized events as a sequence of event images and performed image denoising process. Then, we used the extended 3D partial recursive search (E-3DPRS) method to generate high-performance motion vector field (MVF) between adjacent denoising event images with low computational complexity. MVF reflects the object motion trajectory with high time resolution. Furthermore, MVF is used as a priori information to restore potentially sharp images, which alleviates the highly ill-posed deblurring process. At last, we reconstructed a high frame rate sharp video based on a sharp image sequence and MVFs. Extensive experiments show that our proposed algorithm outperforms the existing state-of-the-art methods and achieves better average feature similarity and structural similarity.

In order to eliminate the noise on the pulse interval of high-speed spike-based image sensor, a pulse interval compensation (PIC) algorithm is proposed. Based on the analysis of the principle of sensor noise generation, a pulse interval error model is constructed and the compensation algorithm is developed. First, raw pulse data is obtained from the sensor system, and then the coefficient matrix is used to compensate the non-uniform pulse interval caused by the dark current. Then, the guided filter separates high-frequency noise from scenes details and the pulse interval compensation matrix is obtained in the corresponding pulse interval. Finally, the pulse interval compensation is performed on the raw pulse data for correction. In static scene experiments, the proposed method is compared with the existing state-of-the-art methods and shows a clear advantage in denoising in both low texture and rich texture scenes. In the experiment to film a turntable at a rotation speed of 2000 r/min, 3000 r/min, 6000 r/min, the average roughness decreases from 0.2830 to 0.2034, 0.2937 to 0.2139 and 0.3252 to 0.2501 respectively. These experiments proved that the proposed method can effectively eliminate the noise of the spike-based image sensor.

In this paper, a method to reduce the effect on image quality caused by the parasitic resistance of column bus in high-resolution cMOS image sensors is presented. Through the mathematical model of the column bus, the effect on image quality caused by the resistance is analyzed. The resistance would cause two nonideal factors: dynamic swing reduction and nonlinearity. To reduce the effect of the nonideal factors, this paper utilizes a layout design by putting the readout circuit and column bias circuit on different sides of the pixel array. The relationship among the resistance, light intensity of input, and standard deviation of output gray levels is analyzed. In a 0.13-μm CMOS process and a 12 cm × 12 cm pixel array, the simulation result shows that the resistance would cause column stripes or gradient under a traditional method. Under the proposed method, the peak standard deviation under uniform illumination decreases from 16.25 to 1.44. The peak signal-to-noise ratio increases from 64.66 to 91.64 dB and the structural similarity index increases from 0.79 to 0.97. The proposed method can enhance image quality for high-resolution image sensors significantly.

A two-step analog accumulator structure, fit for CMOS time-delay integration image sensor, is proposed to combat the impacts of parasitic phenomenon of the traditional one-step analog accumulator. To implement the two-step accumulation, the exposure signals are divided into groups. The synchronous signals in each group are integrated in step1 integrators, which are designed based on the switched-capacitor amplifier. Then, the integral signals from step1 are integrated in step2 integrators. The temporal undersampling exposure method is adopted in the sensor to reduce the number of integrators. Two versions of a prototype 64-stage two-step accumulator, with and without the decoupling capacitance Cd, are designed and fabricated in 0.18-μm one-poly four-metal 1.8 V/3.3 V CMOS technology. With an 8×8 stepping pattern, the signal-to-noise ratio improvements of the two versions are 17.278 and 17.192 dB at 64 stages, respectively, while the ideal value is 18.062 dB. The experimental results have proved the effectiveness of the two-step structure in combating the parasitic phenomenon and made the analog accumulator with higher stage realizable.

This brief presents a 32-stage CMOS time delay integration image sensor with on-chip column parallel analog accumulator. Temporal oversampling technique is applied in the sensor to realize synchronous signal capturing. A column parallel analog accumulator with layout size of 0.09 mm2is integrated at both sides of pixel array. Through adopting input-offset storing technique, a column fixed pattern noise because of the amplifier's offset variations is reduced by the accumulator. The accumulator also acts as a pixel noise canceller. The fabricated chip in 0.18- μm one-poly four-metal 1.8/3.3-V CMOS technology achieves the maximum line rate of 3875 lines/s. The measured signal-to-noise ratio of the fabricated sensor is improved on average by 11.9 dB at 16 stages and 14.2 dB at 32 stages. The presented sensor is suitable for application in low illumination, high scanning speed, and remote sensing systems.