This paper presents a compact high-voltage switched-capacitor (SC) MEMS actuator driver. Specifically, an exponential SC boost stage provides a high step-up voltage conversion ratio (VCR), followed by a series-parallel (SP) SC stage to sequentially drive the load step by step for efficient reactive power delivery while complying with the voltage rating of passive components. With a reduced number of operating steps as well as passive components, the proposed SC driver can effectively enable a high MEMS driving efficiency with a smaller volume, lighter weight, and lower cost. The reduced number of steps also ensures a higher driving frequency, improving the maximum reactive output power. Fabricated in a standard 180nm BCD process, the chip prototype can efficiently transfer reactive power up to 683mW, while achieving a ~3× power density improvement when compared with similar prior arts.

This paper presents a fully integrated single-input-dual-output (SIDO) SC DC-DC converter targeting on fast dynamic voltage scaling (DVS) and fast transient response applications. By applying the proposed cell-level 3-step transition sequence with multi-phase interleaving, this work can enable multiple output CLOAD-free operation with fast and robust dynamic voltage scaling (DVS) operation. The proposed PFM loop with on-demand S/H and power boundary control, together with the load transient enhancement control can also ensure dynamic power cell allocation to achieve full power utilization and a fast load transient response. Fabricated in standard 65nm CMOS, the proposed converter achieves SIDO operation with step-down VCRs of 5:4/3/2/1. At VIN= 1.2V, this work achieves a measured peak power conversion efficiency (PCE) of 83%, a fast DVS speed of 263.8mV/ns, and a fast transient recovery time of 19.8ns. It also demonstrates a measured PCE improvement of up to 6.7% under full power cell utilization.

Machine learning models often suffer from performance degradation when dealing with class distributions that differ from the training distribution, a scenario commonly referred to as label shift. Addressing this challenge, this paper introduces Match, a novel adjustment approach that maximizes the likelihood of predicted probabilities under class prevalence constraints. Unlike existing methods such as retraining with instance re-weighting and the Bayes update rule, Match ensures that the adjusted class distribution aligns precisely with the prevalence estimates from quantifiers. By formulating the adjustment process as a binary integer linear optimization problem, Match benefits from efficient mixed-integer solvers. Extensive experiments demonstrate that Match outperforms the state-of-the-art in classifier adjustment with statistical significance, particularly in handling scenarios with imbalanced distributions.

Bluetooth Low Energy (BLE) backscatter is a promising candidate for battery-free Internet of Things (IoT) applications. We propose PassiveBLE, a backscatter system that can establish authentic and fully compatible BLE connections on data channels. The key enabling techniques include (i) a synchronization circuit that can wake up tags and activate backscatter communications with symbol-level accuracy to facilitate BLE data packet generation; (ii) a distributed coding scheme that offloads the major encoding and processing burdens from tags to the excitation source while achieving high throughput; (iii) a BLE connection scheduler to enable fully compatible BLE connection interactions, including connection establishment, maintenance and termination for multiple backscatter tags. We prototype PassiveBLE tags with off-the-shelf components and also conduct comprehensive experiments to evaluate the performance. Results demonstrate that PassiveBLE achieves a success rate of over 99.9% in establishing commodity BLE connections. PassiveBLE also achieves commodity-compatible BLE communication with a high goodput of up to 974 kbps in LE 2M PHY mode and 532 kbps in LE 1M PHY mode, which is about 63.3× higher than existing commodity-level BLE backscatter system in the same mode.

This paper presents a fully integrated single-input-dual-output (SIDO) switched-capacitor (SC) DC-DC converter targeting on fast dynamic voltage scaling (DVS) and fast transient response applications. By applying the proposed cell-level 3-step transition sequence with multi-phase interleaving, this work can enable multiple output${C} _{\mathbf {LOAD}}$-free operation with fast and robust DVS operation. The proposed pulse frequency modulation (PFM) loop with power boundary control also supports on-demand sample-and-hold (S/H) operation and load transient enhancement technique to ensure full power utilization while exhibiting robust DVS transition and fast transient response. Fabricated in standard 65nm CMOS, the proposed SC converter achieves SIDO operation with flexible step-down VCRs of 5:4/3/2/1. At${V} _{\mathbf {IN}} =1.2$V, this work achieves a measured peak power conversion efficiency (PCE) of 83%, a fast DVS speed of 263.8mV/ns, and a fast transient recovery time of 19.8ns.