Multipatterning technology used in 7-nm technology and beyond imposes more and more complex design rules on the layout of cells. The often nonlocal nature of these new design rules is a great challenge not only for human designers but also for existing algorithms. We present a new flow for automatic cell layout generation that is able to deal with these challenges by globally optimizing several design objectives simultaneously. Our transistor placement algorithm not only minimizes the total cell area but at the same time guarantees the routability of the cell and finds a best arrangement and folding of the transistors. Our routing engine computes a detailed routing of all nets simultaneously. It computes a netlength optimal routing using a mixed-integer programming formulation. Additional DFM constraints are added to this model to improve yield and reduce chip manufacturing costs. We present experimental results on current 7-nm designs. Our approach allows to compute optimized layouts within a few minutes, even for large complex cells. The algorithms are used for the design of logic cells compatible with a published 7-nm technology from a leading chip manufacturer where they meet manufacturability requirements and significantly reduced design turn around times.