Resistive random access memory (RRAM) crossbar arrays enable analog in-memory computing, promising high parallelism and reduced data transfer for deep neural networks (DNNs) inference. However, when many columns share a single time-multiplexed analog-to-digital converter (ADC), readout latency, dominated by serialized conversion, can become a performance bottleneck. This article presents the First-Settle, First-Convert (FSFC) readout architecture, a readiness-driven ADC scheduling scheme for RRAM-based fully connected neural networks (FCNNs). Conventional crossbar readout relies on global settling, where all bitlines must wait for the slowest column to stabilize before sequential conversion begins. FSFC replaces this schedule with per-column readiness detection and a priority-queue encoder that continuously routes the earliest-settled column to the shared ADC, overlapping bitline settling and conversion without adding extra ADCs or changing the crossbar. Software experiments and SPICE-level circuit simulations in SkyWater 130 nm show that FSFC reduces inference latency by 35%–67% across 1- to 8-bit quantized MNIST FCNNs, with no loss of classification accuracy. A transistor-level implementation of the differentiator, hysteresis comparator, and digital priority-queue encoder incurs about 80 pJ of control energy per matrix-vector multiplication (MVM) for a$30\times 10$array, scaling to approximately 1 nJ per MVM and about 5%–8% tile area overhead for a 128-column tile. Because FSFC shortens ADC active time while introducing only modest peripheral circuitry, it provides a low-cost, drop-in latency improvement for RRAM compute-in-memory (CIM) tiles. The technique is orthogonal to existing ADC pooling, precision-reduction, and analog-cascading schemes, and can be integrated as a readout front-end in future crossbar-based accelerators.

This article presents a new and novel nonoverlapping clock (NOC) generator based on a laddered inverter (LI) circuit. Unlike conventional approaches, the proposed NOC combines the clock generation and pulsewidth-modulation (PWM) circuit into one integrated architecture, offering lower power consumption, smaller area, and a more robust solution. Furthermore, the proposed NOC offers an inherent guarantee of the nonoverlap (dead time) between the output signals thanks to the guaranteed monotonicity of the LI circuit, thus offering a layout-agnostic design. The proposed NOC can also offer dead-time reconfigurability with the help of multiplexers, allowing both calibration and fine-tuning of the dead times to meet specific requirements. We provide a comprehensive assessment of the proposed NOC through simulation and measurement results in 65-nm CMOS. Measured results show that the proposed NOC consumes$1~\mu $W at 5 MHz with a 1-V supply, achieving more than$10\times $lower power consumption and 25% smaller area compared to the conventional NOC circuit. The proposed NOC demonstrates the capability to generate waveforms with frequencies up to 3.5 GHz at a 1.2-V supply, as validated through simulations.

This paper develops a computationally efficient model for automatic patient-specific seizure prediction using a two-layer LSTM from multichannel intracranial electroencephalogram time-series data. We decrease the number of parameters by employing a smaller input size and fewer electrodes, thereby making the model a viable option for wearable and implantable devices. We test the proposed prediction model on 26 patients from the European iEEG dataset, which is the largest epileptic seizure dataset. We also apply an automatic preprocessing technique based on a common average reference to remove artifacts from this dataset. The simulation results show that the model with its simple structure in conjunction with the mean post-processing procedure performed the best, with an average AUC of 0.885. This study is the first that utilizes the European database for epilepsy prediction application and the first that analyzes the effect of the seizure type on the system performance and demonstrates that the seizure type has a considerable impact.

This paper presents a radio architecture for 5G Vehicle to Everything (V2X) applications. A frequency planning suitable for the aforementioned radio architecture is proposed. A programmable Time-Interleaved (TI) Successive Approximation Register (SAR) Analog to Digital Converter (ADC) required for this radio architecture is presented. The effect of process and temperature (PT) variations on the performance of Monotonic SAR ADC is investigated. A calibration technique is proposed to account for PT variations in the Monotonic SAR ADC. Additionally, simulation results for TI SAR ADC designed in 22nm FDSOI which works at two different sampling frequencies for V2X applications are presented.

This paper presents a comprehensive analysis of hardware accelerators for neural networks in both the digital and time domains, where the latter includes spatially unrolled (SU) and recursive (REC) architectures. All accelerators are implemented and synthesized in a 65nm CMOS technology. An identical neural network model is implemented in the digital and time domain for comparative purposes in terms of throughput, power consumption, area, and energy efficiency. Post-synthesis results show that SU achieves the highest energy efficiency of 145 TOp/s/W with a throughput of 4 GOp/s. The digital core is the fastest among other cores, whereas REC is the slowest but is the most area-efficient, occupying 0.114 mm2. SU is more suited for applications with stringent power constraints and average performance, while REC is better suited for applications where the area is the most important requirement and the throughput is less significant. In contrast, the digital core is preferable for large neural networks and critical applications that require high performance.

This paper provides a comprehensive analysis of the available EEG datasets that are used for epilepsy prediction systems, including Melbourne, CHB-MIT, American Epilepsy Society, Bonn, and European Epilepsy datasets. These datasets are compared in terms of the sampling rate, number of patients, recording time, number of channels, artifacts, and types of EEG signals. We also provide details on the challenges of using one dataset over the others in predicting epilepsy. Subsequently, we compare the performance of various machine learning models that use these datasets for epileptic seizure prediction. This is the first work that provides a comprehensive analysis of various EEG datasets and should be of great importance for researchers in EEG-based systems for epileptic seizure prediction.

This paper presents a single-stage power management unit to boost and regulate a low supply voltage for CMOS system-on-chip (SoC) applications. It consists of low-leakage, enhanced Dickson charge pump (DCP) that utilizes both stage and frequency modulation (FM) techniques to achieve high efficiency and lower area. In addition, the proposed design uses an enhanced stage-switch structure for the charge pump, which significantly reduces the cross-stage leakage. A stage number controller is used to control the gain of the charge pump by changing the number of stages based on the desired output voltage. FM is utilized to further fine-tune the output voltage through a closed-loop control based on a predetermined reference voltage. Silicon measurement results for the four-stage charge pump in 65-nm CMOS technology show a maximum end-to-end efficiency of 66% at an input voltage of 0.7 V and an output power of$27~\mu \text{W}$. The proposed design achieved more than a$100\times $reduction in leakage compared to traditional DCP. The system supports a range of load currents between 0.1 and$34~\mu \text{A}$with a maximum operating frequency of 1.8 MHz. The proposed system supports an input voltage range of 0.55–0.7 V which makes it an excellent candidate for solar and thermal energy-harvesting applications targeting low-power internet-of-things SOC.

This paper presents an area and power efficient multioutput switched capacitor (MOSC) DC-DC buck converter targeting ultra-low power and IoT devices. The MOSC converter has a variable input voltage range between 1.05V to 1.4V and generates regulated simultaneous multiple output voltage levels of 1V and 0.55V. Adaptive digital time multiplexing controller is employed to enable multiple power domains. In addition, a pulse frequency modulation is utilized to regulate the output voltages over a wide range of load current. The proposed converter supports a load current of 10μA to 350μA and to 10μA at a load voltage of 1V and 0.55V, respectively. Adaptive time multiplexing and pulse width modulation are implemented through a finite state machine to eliminate the reverse current issue. This problem arises during the switching from a low load voltage of 0.55V to a high load voltage of 1V. The MOSC circuit is fabricated in 65nm CMOS technology and it occupies an active area of 0.27mm2. Moreover, both MIM and MOS capacitors are utilized to further reduce the area of MOSC converter. Measured results shows that the peak efficiency of 78% is achieved at a load power of 300μW.

This paper presents a single stage power management unit that includes an enhanced stage-switch Dickson charge pump (DCP) to boost and regulate a low input voltage. A new switching mechanism is presented to significantly reduce the losses encountered in conventional DCP switches. Frequency and stage modulation are utilized in the proposed design. The stage modulation provides different gain levels (coarse) and the frequency modulation tunes the voltage level and regulates the output voltage based on a pre-determined reference voltage. Using four stages charge pump, silicon measurement results in 65 nm CMOS technology show a maximum efficiency of 66% at input voltage of 0.7 V and output power of 27 μW. The system supports a range of load current between 0.1 μA − 34 μA with a maximum operating frequency of 1.8MHz. The proposed system supports an input voltage range from 0.55 to 0.7 V which can be used in energy harvesting applications such as solar and thermal harvesting.

This paper presents an efficient thermal energy harvesting IC (EHIC) that supports a battery-less μWatt system-on-chips. The EHIC consists of an inductor-based DC-DC converter that boosts a low input voltage to a suitable output voltage level. Further, a switched capacitor buck converter is utilized to regulate the boost converter output voltage and to support multiple output voltage levels, namely 0.6V, 0.8V and 1V. In low energy mode and to enhance the efficiency, the EHIC is capable of bypassing the switched capacitor so that the load is driven directly from the boost converter. The prototype chip is fabricated in 65nm CMOS and occupies an area of less than 0.46mm2. Measured results confirm an efficiency of 65% at 0.6V output voltage and 42μW. In addition, the end-to-end peak efficiency is 71% at 0.8V output voltage and 182μW.

A CMOS analog circuit topology is presented that provides a number of stable operating points based on a laddered inverter quantizer (LIQAF) circuit. An input voltage sets the initial voltage state value when a CMOS transmission gate is turned on, and the voltage state then settles to the nearest stable operating point once the CMOS transmission gate is turned off. The proposed analog circuit achieves its stable operating levels through nonlinear, continuous-time feedback with a circuit that requires only a single supply voltage. An IC prototype demonstrates a 10-level version of the multi-stable circuit with an area of 0.015mm2in 0.18μm CMOS and current consumption of 300μA at 1.4V and <;45μA at 1V supply for a pair of the multi-stable circuits.