Due to the continuous shrinking of technology nodes, the minimum implant area (MIA) constraint has become a critical issue for modern circuit placement. With a fixed cell height, this constraint can be transferred into a minimum cell width constraint, and thus cells of small widths may have MIA violations. To solve such violations, we may shift neighboring cells to preserve whitespace or abut violating cells with the same threshold voltages (VTs). This paper presents an MIA-aware detailed placement algorithm to effectively solve the placement problem with the MIA constraint by clustering violating cells with the same VTs, and then apply cluster-based detailed placement algorithms to solve this problem. To further minimize the design area, an MIA-aware cell flipping algorithm based on linear-time dynamic programming is presented. Experimental results show that our algorithm can achieve high-quality results for this problem and is very robust for different multi-VT designs and MIA constraints.

Layout-dependent effects (LDEs) have become a critical issue in modern analog and mixed-signal circuit designs. The three major sources of LDEs, well proximity, length of oxide diffusion, and oxide-to-oxide spacing, significantly affect the threshold voltage and mobility of devices in advanced technology nodes. In this paper, we propose the first work to consider the three major sources of LDEs during analog placement. We first transform the three LDE models into nonlinear analytical placement models. Then an LDE-aware analytical analog placement algorithm is presented to mitigate the influence of the LDEs while improving circuit performance. Experimental results show that our placement algorithm can effectively and efficiently reduce the LDE-induced variations and improve circuit performance.

Due to the significant mismatch between global-routing congestions estimated during placement and the resulting design-rule violations in detailed routing, considering both global and detailed routability during placement is of particular importance for modern circuit designs. This paper presents an analytical standard-cell placement algorithm to optimize detailed routability with three major techniques: (1) A routability-driven wirelength model that directly minimizes routing congestion and wirelength simultaneously with no additional computational overhead in global placement. (2) A detailed-routability-aware whitespace allocation technique in legalization. (3) A multi-stage congestion-aware cell spreading method in detailed placement. Compared with the participating teams of the 2014 ISPD Detailed-Routing-Driven Placement Contest and a state-of-the-art routability-driven placer, our placer achieves the best quality in both detailed-routing violation and wirelength scores.

Self-aligned double patterning (SADP) with complementary e-beam lithography (EBL) is one of the most promising hybrid-lithography techniques for sub-20nm designs. The complementary EBL mitigates the deficiencies of using a single cut mask in SADP. However, the low throughput and negative side effects of EBL might significantly increase the manufacturing costs and damage the symmetry properties in analog circuits. In this paper, we present the first work that considers SADP with EBL during analog placement to simultaneously optimize the area, wirelength, overlay errors, and e-beam shots. We first propose an overlay and cut conflict-aware SADP decomposition algorithm to optimize the overlay errors and e-beam shots in a layout. Then, a dynamic programming based module shifting technique is developed based on a symmetry-feasible slicing tree formulation to further minimize the differences of overlay errors and e-beam shots between symmetry modules during analog placement. To explore and obtain a desired placement, an analog placement flow is also presented. Experimental results show that our flow can effectively and efficiently reduce area, overlay errors, and e-beam shots while satisfying the symmetry constraints for analog placement.

Layout-dependent effects (LDEs) have become a critical issue in modern analog and mixed-signal circuit designs. The three major sources of LDEs, well proximity, length of oxide diffusion, and oxide-to-oxide spacing, significantly affect the threshold voltage and mobility of devices. In this paper, we propose the first work to consider the three major sources of LDEs during analog placement. We first transform the three LDE models into nonlinear analytical placement models. Then an LDE-aware analytical analog placement algorithm is presented to mitigate the influence of the LDEs while improving circuit performance. Experimental results show that our placement algorithm can effectively and efficiently reduce the LDE-induced variations and improve circuit performance.

Designs of flow-based microfluidic biochips are receiving much attention recently because they replace conventional biological automation paradigm and are able to integrate different biochemical analysis functions on a chip. However, as the design complexity increases, a flow-based microfluidic biochip needs more chip-integrated micro-valves, i.e., the basic unit of fluid-handling functionality, to manipulate the fluid flow for biochemical applications. Moreover, frequent switching of micro-valves results in decreased reliability. To minimize the valve-switching activities, we develop a network-flow based resource binding algorithm based on breadth-first search (BFS) and minimum cost maximum flow (MCMF) in architectural-level synthesis. The experimental results show that our methodology not only makes significant reduction of valve-switching activities but also diminishes the application completion time for both real-life applications and a set of synthetic benchmarks.

Designs of flow-based microfluidic biochips have emerged as a popular alternative for laboratory experiments because they replace conventional biochemical paradigms on a chip. As the applications become more complicated, a flow-based microfluidic biochip requires more valves to manipulate the sample flow for the large-scale and concurrent experiments. Despite the design complexity is increased very quickly, current synthesis methodologies still use full custom and bottom-up procedures to synthesize a biochip. These manual steps are time consuming and would lead to dispensable valve-switching. According to recent studies, frequently switching the valves may reduce the reliability. To minimize the valve-switching activities, we propose a top down synthesis methodology for flow-based microfluidic biochip. We develop a set-based minimum cost maximum flow (SMCMF) resource binding algorithm and an incremental cluster expansion (ICE) placement algorithm in architecture-level and physical-level synthesis, respectively. The experimental results show that our methodology not only makes significant reduction of valve-switching amount but also diminishes the application completion time for both real-life applications and a set of synthetic benchmarks.