A delay-locked loop (DLL) circuit is often useful for the clock synchronization in a chip incorporating multiple functional dies. In this work, we present a process-resilient fault-tolerant DLL design. We will first show that a naïve triple-module redundancy (TMR) technique cannot work well unless with a simple yet powerful static timing correction scheme to nullify the adversary effect caused by the voter circuit’s delay. Furthermore, we enhance it with a dynamic scheme so that the overall performance is immune to process variation. Through the proposed schemes, the maximum phase error over 1000 clock cycles between the DLL’s input and output clock signals after locking, which is often considered as the most important performance metric, can be reduced tremendously from 130 ps using only naïve TMR to 20 ps using static timing correction, and then further down to 11 ps using the dynamic timing correction.

In an IC used for safety-critical applications, the Fault and soft-error tolerance (or FET) is often desirable. In this work, we consider a graceful degradation scheme, as the second line of defense, for a FET delay-locked loop (DLL) we have recently developed. By doing so, a FET DLL will not operate blindly when its tolerance to faults or soft errors has been degraded. This is achieved by incorporating a novel low-cost excessive phase-error monitor. Any excessive phase error beyond a prelearned phase-error tolerance range will trigger an alarm of failure. This monitor can also be used to support an online test for deciding whether there is a faulty module in our TMR-based FET DLL at any given time. We have implemented the proposed scheme in a 90-nm CMOS process. The results show that the area of this excessive phase error monitor is as small as 60$\mu \text{m}\,\,\times $60$\mu \text{m}\,\,=$0.0036 mm2, or only 4.12% of the entire FET DLL.

We present in this paper the first fault and soft error tolerant Delay-Locked Loop (DLL) design, useful for the clock synchronization in a chip incorporating heterogeneous functional dies. In this robust DLL design, we introduce a powerful timing correction scheme to remedy the timing shortfall in a naïve Triple-Module Redundancy (TMR) architecture. Post-layout simulation results using a 90nm CMOS process is used to verify the performance of this design. In addition to the tolerance of randomly injected faults or soft errors, the Maximum Phase-Error can be improved tremendously from 117ps to just 17ps by the proposed timing correction scheme.