Self-regulated learning significantly influences students’ academic behavior and performance. Traditional SRL assessment heavily relies on subjective and self-evaluation methods, which are susceptible to personal biases and cognitive limitations. In this study, we leverage mobile devices with GPS and sensors to collect self-reported and passive mobile sensing data from 211 college students over a year. Our aim is to conduct a passive assessment of self-regulated learning. To achieve this, we apply four deep learning models to analyze behavioral features associated with self-regulated learning using students’ life record data. Our findings demonstrate a precise assessment of student self-regulated learning, encompassing the following subscales. Environment structuring (MAE = 2.88, r = 0.54) represents participation in the organization and construction of the learning environment. Time management (MAE = 2.82, r = 0.57) represents planning study time and balancing study with other activities; Help seeking (MAE = 4.86, r = 0.53) represents the tendency and frequency of students to seek help during the learning process. Our study helps inspire new forms of education to assess self-regulated learning and paves the way for individualized interventions in future studies. • We develop and implement the iSense system for SRL assessment. • Collecting mobile sensing and self-reported data from 211 students over a year. • Establishing an SRL assessment model using mobile sensing data and deep learning. • We observe that SRL highly correlates with app usage patterns and sensing data. • Our study can achieve longitudinal monitoring and early intervention of SRL.

Understanding and identifying the nature of learner confusion is important for online learning platforms. In this study, we address this problem by analyzing forum posts from large-scale online courses. However, due to the large volume of comments and frequent interactions, confusion posts are often overlooked. Existing methods and models, while capable of detecting confusion, typically rely on linguistic features of posts and community factors (e.g. votes, views) but ignore personalized contexts, such as the specific causes and types of confusion. To address this problem, we create the first deep learning dataset focused on confusion types and develop a BERT-based network to model personalized features and identify confusion types. Considering the highly imbalanced distribution of different types of confusion, we further design a novel loss function that adaptively optimizes the training weights for each type. Our method’s effectiveness is confirmed through extensive experimentation.

Building accurate Machine Learning (ML) models requires substantial expertise and large-scale datasets typically only available in big data companies. These companies have been selling their models as Machine Learning as a Service. However, concerns about data privacy and the appliance of ML in mission-critical scenarios are forcing ML computation to move from the cloud to the deep edge, near sensor data. If edge ML increases user data privacy and makes decision latency predictable, deploying proprietary ML models on untrusted edge devices may harm the intellectual property of Service Providers. A natural response to this issue comes from Trusted Execution Environments (TEEs), which provide hardware-based security. However, adapting ML computation to the constraints of TEEs remains an open challenge. In this article, we propose SecureQNN, a framework that leverages state-of-the-art TEE technology (TrustZone-M) available in Arm Cortex-M microcontrollers to increase the protection of Quantized Neural Networks (QNNs) against unauthorized replication. SecureQNN evaluates which layers lessen the effort of an attacker when building a surrogate QNN with the same accuracy. The layers making the attacker spend less training epochs than the owner training from scratch are stored and executed in the secure-world of the TEE. Experiments demonstrate that SecureQNN undermines the cost-benefit of unauthorized QNN replication by isolating 51%–65% of the model size while incurring a worst-case decision latency overhead of only 0.06%. Although SecureQNN has broader applicability, the negligible impact on decision latency and its deterministic behavior highlight the suitability of SecureQNN for mission-critical and real-time applications.

Emotion-cause pair extraction (ECPE) main focus is on extracting all potential emotion clauses and corresponding cause clauses from unannotated documents. Existing methods achieve promising results with the help of fine-tuning and prompt paradigms, but they present three downsides. First, most approaches cannot distinguish between the emotion-cause pairs that belong to different types of emotions, limiting the existing approaches’ applicability. Second, existing prompt methods utilize a one-to-one mapping relation to achieve label words to category mapping, which brings considerable bias to the results. Third, existing methods achieve the cause extraction task supported by explicit semantic understanding or basic prompt templates, ignoring the implicit information contained in the cause clauses themselves. To solve these issues, we propose an Emotion knowledge-aware Prompt-tuning for Emotion-Cause Pair Extraction (EmoPrompt-ECPE) method, which integrate the knowledge of emotion categories in the ECPE task and mine the implicit knowledge of cause clauses. Specifically, we inject the latent knowledge of the cause clauses and the emotion types into the prompt template. Besides, we extend the emotion labels for many-to-one mapping of label words to categories with an external emotion word base. Furthermore, we utilize the cosine similarity filtering of the label word base to reduce the noise caused by knowledge introduction. Experiments on both Chinese and English benchmark datasets show that our approach can achieve state-of-the-art results. Our code and data can be found at: https://github.com/xy-xiaotudou/EmoPrompt-ECPE.

Abstract The evergrowing Internet of Things (IoT) ecosystem continues to impose new requirements and constraints on every device. At the edge, low-end devices are getting pressured by increasing workloads and stricter timing deadlines while simultaneously are desired to minimize their power consumption, form factor, and memory footprint. Field-Programmable Gate Arrays (FPGAs) emerge as a possible solution for the increasing demands of the IoT. Reconfigurable IoT platforms enable the offloading of software tasks to hardware, enhancing their performance and determinism. This paper presents ChamelIoT, an agnostic hardware operating systems (OSes) framework for reconfigurable IoT devices. The framework provides hardware acceleration for kernel services of different IoT OSes by leveraging the RISC-V open-source instruction set architecture (ISA). The ChamelIoT hardware accelerator can be deployed in a tightly- or loosely-coupled approach and implements the following kernel services: thread management, scheduling, synchronization mechanisms, and inter-process communication (IPC). ChamelIoT allows developers to run unmodified applications of three well-established OSes, RIOT, Zephyr, and FreeRTOS. The experiments conducted on both coupling approaches consisted of microbenchmarks to measure the API latency, the Thread Metric benchmark suite to evaluated the system performance, and tests to the FPGA resource consumption. The results show that the latency can be reduced up to 92.65% and 89.14% for the tightly- and loosely-coupled approaches, respectively, the jitter removed, and the execution performance increased by 199.49% and 184.85% for both approaches.

There is increasing pressure to optimize Internet of things (IoT) low-end devices. The ever-growing number of requirements and constraints is pushing towards maximizing performance and real-time, but simultaneously minimizing power consumption, form factor, and memory footprint. This has motivated the adoption of Field-Programmable Gate Array (FPGA) technology to accelerate computing-intensive workloads in hardware. However, and despite the ongoing trend of migrating application-level tasks to hardware, recently, the offload of system software such as operating system (OS) services has received little attention. This paper presents CHAMELIOT, a framework for FPGA-based IoT platforms that provides agnostic hardware acceleration to OS services by leveraging RISC-V technology. CHAMELIOT allows for developers to run unmodified applications in a set of well-established IoT OSes. Currently, the framework has support for RIOT, Zephyr, and FreeRTOS. The evaluation showed that latency and determinism can be enhanced up to 10x while the system’s performance can be increased to nearly 200%. CHAMELIOT will be open-sourced.

Capsule networks (CapsNets) are an emerging trend in image processing. In contrast to a convolutional neural network, CapsNets are not vulnerable to object deformation, as the relative spatial information of the objects is preserved across the network. However, their complexity is mainly related to the capsule structure and the dynamic routing mechanism, which makes it almost unreasonable to deploy a CapsNet, in its original form, in a resource-constrained device powered by a small microcontroller (MCU). In an era where intelligence is rapidly shifting from the cloud to the edge, this high complexity imposes serious challenges to the adoption of CapsNets at the very edge. To tackle this issue, we present an API for the execution of quantized CapsNets in Arm Cortex-M and RISC-V MCUs. Our software kernels extend the Arm CMSIS-NN and RISC-V PULP-NN to support capsule operations with 8-bit integers as operands. Along with it, we propose a framework to perform post-training quantization of a CapsNet. Results show a reduction in memory footprint of almost 75%, with accuracy loss ranging from 0.07% to 0.18%. In terms of throughput, our Arm Cortex-M API enables the execution of primary capsule and capsule layers with medium-sized kernels in just 119.94 and 90.60 ms, respectively (STM32H755ZIT6U, Cortex-M7 @ 480 MHz). For the GAP-8 SoC (RISC-V RV32IMCXpulp @ 170 MHz), the latency drops to 7.02 and 38.03 ms, respectively.

Nowadays, and more than a decade after the first steps towards autonomous driving, we keep heading to achieve fully autonomous vehicles on our roads, with LiDAR sensors being a key instrument for the success of this technology. Such advances trigger the emergence of new players in the automotive industry, and along with car manufacturers, this sector represents a multibillion-dollar market where everyone wants to take a share. To understand recent advances and technologies behind LiDAR, this article presents a survey on LiDAR sensors for the automotive industry. With this work, we show the measurement principles and imaging techniques currently being used, going through a review of commercial systems and development solutions available in the market today. Furthermore, we highlight the current and future challenges, providing insights on how both research and industry can step towards better LiDAR solutions.

Arm TrustZone is a hardware technology that adds significant value to the ongoing security picture. TrustZone-based systems typically consolidate multiple environments into the same platform, requiring resources to be shared among them. Currently, hardware devices on TrustZone-enabled system-on-chip (SoC) solutions can only be configured as secure or non-secure, which means the dual-world concept of TrustZone is not spread to the inner logic of the devices. The traditional passthrough model dictates that both worlds cannot use the same device concurrently. Furthermore, existing shared device access methods have been proven to cause a negative impact on the overall system in terms of security and performance. This work introduces the concept of self-secured devices, a novel approach for shared device access in TrustZone-based architectures. This concept extends the TrustZone dual-world model to the device itself, providing a secure and non-secure logical interface in a single device instance. The solution was deployed and evaluated on the LTZVisor, an open-source and lightweight TrustZone-assisted hypervisor . The obtained results are encouraging, demonstrating that our solution requires only a few additional hardware resources when compared with the native device implementation, while providing a secure solution for device sharing.

The Internet of Things (IoT) is enabling the connection of an infinity of physical objects to the Internet through the wide deployment of low-end embedded devices at the network edge. However, providing communication capabilities to such devices, which allows them to connect to the Internet seamlessly, is not straightforward. Such features require the adoption of a lightweight and standard network stack, commonly integrated with an embedded operating system (OS), mitigating the complexity of developing resource-constrained wireless nodes. To assist in such tasks, some existing motes explore reconfigurable technology to accelerate compute-intense tasks (application- or network-related) in dedicated hardware accelerators. This article describes the deployment of a real-time OS, RIOT, on a reconfigurable end-device architecture for IoT, the CUTE Mote. The CUTE mote is based on a heterogeneous solution that combines a hard-core microcontroller unit beside reconfigurable technology and an IEEE 802.15.4-compliant radio transceiver.

Computer systems are permanently present in our daily basis in a wide range of applications. In systems with mixed-criticality requirements, e.g., autonomous driving or aerospace applications, devices are expected to continue operating properly even in the event of a failure. An approach to improve the robustness of the device's operation lies in enabling fault-tolerant mechanisms during the system's design. This article proposes Lock-V, a heterogeneous architecture that explores a Dual-Core Lockstep (DCLS) fault-tolerance technique in two different processing units: a hard-core Arm Cortex-A9 and a soft-core RISC-V-based processor. It resorts a System-on-Chip (SoC) solution with software programmability (available trough the hard-core Arm Cortex-A9) and field-programmable gate array (FPGA) technology, taking advantages from the latter to support the deployment of the RISC-V soft-core along with dedicated hardware accelerators towards the realization of the DCLS.

In the era of the Internet of Things (IoT), billions of wirelessly connected embedded devices rapidly became part of our daily lives. As a key tool for each Internet-enabled object, embedded operating systems (OSes) provide a set of services and abstractions which eases the development and speedups the deployment of IoT solutions at scale. This article starts by discussing the requirements of an IoT-enabled OS, taking into consideration the major concerns when developing solutions at the network edge, followed by a deep comparative analysis and benchmarking on Contiki-NG, RIOT, and Zephyr. Such OSes were considered as the best representative of their class considering the main key-points that best define an OS for resource-constrained IoT devices: low-power consumption, real-time capabilities, security awareness, interoperability, and connectivity. While evaluating each OS under different network conditions, the gathered results revealed distinct behaviors for each OS feature, mainly due to differences in kernel and network stack implementations.

This letter proposes ChamelIoT, an agnostic operating system (OS) framework for reconfigurable Internet of Things (IoT) devices. ChamelIoT is bringing a reconfigurable hardware OS stack supported by a semantically enriched infrastructure that aims at offering an easy-to-use tool for building (mainly) low-power and low-cost IoT sensors with performance, real-time, and power consumption advantages.

Approaches to Dynamic Binary Translation (DBT) on resource-constrained embedded systems are not straight forward, leading to several improvements and acceleration suggestions that rely on dedicated hardware. Software to hardware of-floading is a common acceleration procedure used when software-only approaches do not meet the performance requirements, making such approach suitable to be successfully applied to DBT. This article approaches hardware offloading to address some limitations of an in-house DBT engine, the DBTOR, regarding its Translation Cache (TCache) management mechanism. The suggested approaches are non-intrusive to the target architecture, which cope with the commercial-off-the-shelf (COTS)-driven deployment of DBT for the resource-constrained embedded devices. This work proposes a TCache management hardware module that overpasses the linked list and hash table software-only approaches, resulting in a performance improvement of 25% and 26%, respectively.

The Internet of Things (IoT) is revolutionizing the Internet of the future and the way smart devices, people, and processes interact with each other. Challenges in endpoint devices (EDs) communication are due not only to the security and privacy-related requirements but also due to the ever-growing amount of data transferred over the network that needs to be handled, which can considerably reduce the system availability to perform other tasks. This paper presents an IPv6 over low power wireless personal area networks (6LoWPAN) accelerator for the IP-based IoT networks, which is able to process and filter IPv6 packets received by an IEEE 802.15.4 radio transceiver without interrupting the microcontroller. It offers nearly 13.24% of performance overhead reduction for the packet processing and the address filtering tasks, while guaranteeing full system availability when unwanted packets are received and discarded. The contribution is meant to be deployed on heterogeneous EDs at the network edge, which include on the same architecture, field-programmable gate array (FPGA) technology beside a microcontroller and an IEEE 802.15.4-compliant radio transceiver. Performed evaluations include the low FPGA hardware resources utilization and the energy consumption analysis when the processing and accepting/rejection of a received packet is performed by the 6LoWPAN accelerator.

Virtualization technology starts becoming more and more widespread in the embedded systems arena, driven by the upward trend for integrating multiple environments into the same hardware platform. The penalties incurred by standard software-based virtualization, altogether with the strict timing requirements imposed by real-time virtualization are pushing research towards hardware-assisted solutions. Among existing commercial off-the-shelf (COTS) technologies, ARM TrustZone promises to be a game-changer for virtualization, despite of this technology still being seen with a lot of obscurity and scepticism. In this paper we present a Lightweight TrustZone-assisted Hypervisor (LTZVisor) as a tool to understand, evaluate and discuss the benefits and limitations of using TrustZone hardware to assist virtualization. We demonstrate how TrustZone can be adequately exploited for meeting the real-time needs, while presenting a low performance cost on running unmodified rich operating systems. While ARM continues to spread TrustZone technology from the applications processors to the smallest of microcontrollers, it is undeniable that this technology is gaining an increasing relevance. Our intent is to encourage research and drive the next generation of TrustZone-assisted virtualization solutions.

With the increased complexity of low-end devices in the Internet of Things (IoT), mainly due to the connectivity and interoperability requirements, the development and configuration of embedded operating systems (OSes) for such devices is not straight forward. The complexity of the communication requirements is usually mitigated by the OS, e.g., the Contiki-OS, as it already incorporates an IoT-compliant network stack. Yet, the configuration of such stack requires major knowledge on the code structure, leading to additional development time, particularly when the network comprises several wireless nodes and individual configurations with subsequent firmware that needs to be generated. Based on a developed software modeling domain-specific language, this paper presents the EL4IoT framework. It aims to reduce and ease the development time by promoting a design automation tool that can configure, and automatically generate code (ready to compile) for low-end IoT devices running the Contiki-OS. Although leveraging the whole Contiki-OS modeling, this work only refactored and modeled the network stack while approaching the OS itself as one big building block or component. The proposed approach can be extended to other IoT-enabled OSes as well as integrated in other design automation tools.

Industrial solutions design is a highly complex topic due to the challenge of integrating multiple technologies into a single solution, the inherent complexity of the problems to be solved and also because the proposed solutions often require a great level of interoperability among their components and also the outside world. Dynamic Binary Translation has been used as a tool to deal with such interoperability issues, e.g., legacy support, virtualization and secure execution, among others. However its integration in the industry as an end-product is hampered by the intricate variability management required in this subject. To address these issues and in an attempt to power DBT utilization as an interoperability-providing tool, we propose a model-driven DSL modeling language for DBT architectures. The developed DSL proved to be efficient to model an in-house DBT engine, and MODELA DBT, a framework for ready-to-use DBT solutions was obtained. MODELA DBT provides design validation, easy configuration of customizable DBT parameters and components, as well as code generation features.

In the near future, billions of new smart devices will connect the big network of the Internet of Things, playing an important key role in our daily life. Allowing IPv6 on the low-power resource constrained devices will lead research to focus on novel approaches that aim to improve the efficiency, security and performance of the 6LoWPAN adaptation layer. This work in progress paper proposes a hardware-based Network Packet Filtering (NPF) and an IPv6 Link-local address calculator which is able to filter the received IPv6 packets, offering nearly 18% overhead reduction. The goal is to obtain a System-on-Chip implementation that can be deployed in future IEEE 802.15.4 radio modules.

Multithreading is a key feature for dealing with the complexity of current generation embedded devices. Real-Time Operating Systems (RTOSes) provide a higher level of abstraction that alleviates design complexity and time-to-market pressure, inducing, however, undesired latencies and unpredictable execution times. Research works have been focusing on improving performance, determinism or agnosticism, but none simultaneously tackled the three metrics. This work in progress paper presents RT-SHADOWS, a co-designed architecture that promotes configurability, determinism and agnosticism from the outset. A multi-thread ARM softcore processor was exploited and extended by offloading the scheduling-related features into the hardware layer. The hardware multi-thread support is transparent for the standard RTOS applications and independent of the Operating System (OS). Promising preliminary results demonstrate huge improvements on performance and determinism, with only a small cost on hardware.

With the growing ubiquity of Internet of Things (IoT), myriads of smart devices connect and share important information over the Internet. In order to provide connectivity and interoperability of all the existing heterogeneous wireless devices, a full communication stack is proposed by the IoT Architecture Reference Model (IoT-ARM). From the sensor to the cloud, the proposed stack can be implemented on all IoT devices avoiding the battle for the wireless standard that will be adopted. This work in progress paper proposes an FPGA-based edge device for IoT, which uses SoC (System-on-Chip) FPGA technology to offload critical features of the communication stack to dedicated hardware, aiming to increase systems performance.

Migration to multicore is inevitable. To harness the potential of this technology, embedded system designers need to have available operating systems (OSes) with built-in capabilities for multicore hardware. When designed to meet real-time requirements, multicore SMP (Symmetric Multiprocessing) OSes not only face the inherent problem of concurrent access to shared kernel resources, but still suffer from a bifid priority space, dictated by the co-existence of threads and interrupts. This work in progress paper presents the offloading of the FreeRTOS kernel components to a commercial-off-the-shelf (COTS) multicore hardware. The ARM Generic Interrupt Controller (GIC) is exploited to implement a multicore hardware-centric version of the FreeRTOS that not only solves the priority inversion problem, but also removes the need of internal software synchronization points. Promising preliminary results on performance and determinism are presented, and the research roadmap is discussed.

The usage and deployment of Wireless Sensor Networks (WSN) is rapidly increasing in many different monitoring and control applications. In the majority of these applications, energy is a key factor in sensor networks since the sensor nodes are battery powered and hence have limited resources of energy. In this context, choosing a proper energy-efficient routing technique can increase the network life time. In this paper, a new Hybrid Energy-Efficient (HEE) routing protocol is proposed. HEE uses Direct Transmission (DT) and Minimum Energy Transmission (MTE) which are two of the simplest methods in terms of computational complexity. However the design of routing techniques is highly dependent on the application and the performance may vary based on environmental parameters. The novel proposed method is applicable for different networks regardless of the size and distances between the nodes and also with different parameters such as number of nodes and message length. Simulation results show how HEE performs more efficiently in terms of energy consumption when comparing to DT and MTE.

Wireless Sensor Networks are an emerging technology which has been recently adopted in many applications. Due to its wireless nature, the analysis of the radio propagation models plays an important role for performance evaluation in both theoretical and practical aspects. In this regards, path loss exponent is one of the most important parameter which has been considered widely in wireless communications analysis. There are several theoretical evaluations of path loss exponent for wireless sensor networks available in the literature. However there is a lack of experimental evaluation of both path loss exponent and the effect of shadowing. In this paper, three environments (free space, in building and industrial), where wireless sensor nodes are widely deployed, have been chosen in order to evaluate the experimental analysis. Path loss and path loss exponent are measured by means of Received Signal Strength Indicator (RSSI) and based on them, the standard deviation of shadowing effect is also calculated. All the measured parameters are compared with the theoretical analysis available in the literatures.

The proliferation of highly-configurable FPGA technology has allowed the implementation of dedicated systems of diverse configurations and fueled the software to hardware migration paradigm. This work demonstrates how the hardware implementation of virtualization technology affects the system reliability at several levels of abstraction. By correlating faults between the physical and virtual, the reliability impact of hardware-assisted virtualization is shown, as well as how runtime faults are capable of breaching virtualization. ISA profiling is used to assess reliability at early design stages and how its use can serve as a robustness guideline for hardware and software designers is explained.

This paper presents an innovative Multi Processor System on Chip (MPSoC) architecture based on Service Oriented Architecture (SOA) concepts. The proposed architecture promotes the design flexibility and interoperability by setting an implementation agnostic services' integration interface and being reconfiguration aware by design. The concept is tried with an example of an embedded legacy support system, a Dynamic Binary Translation (DBT) engine based on three services. DBT can solve the x86 architecture virtualization limitations. A SOA based MPSoC endowed of autonomous dynamic reconfiguration capabilities is introduced and pointed as a research opportunity. The introduction in the architecture of a Service Module responsible for Partial Runtime Reconfiguration (PRTR) is expected to dynamically adjust the architecture to better match the workload.

The heterogeneity of device interfaces and the disparity between interconnection standards leads to difficulty in achieving seamless device interoperability. The Open Services Gateway Initiative (OSGi) framework attempts to provide a unified Residential Service gateway by abstracting from the device interface and providing transparent methods for Service Oriented Architectures. However, it is not yet compliant with all standards and unsuited for some. This paper presents the development of a Multi-Camera Home Network System, using devices which implement three different protocols. The OSGi gateway bundles to handle the interoperability are described including one OSGi bundle for ONVIF devices. A Residential Service OSGi gateway is also presented and the difficulties faced with the integration of video streaming on the framework are presented, as well as the solutions used to tackle the problem.