We introduce BIONIC (duraBle tImekeeper fOr iNtermIttent Computing), a novel power system architecture and software runtime that facilitates time-sensitive intermittent computing for battery-less Internet of Things. BIONIC integrates timekeeping into energy storage hardware: its power system comprises two energy storage capacitors. BIONIC switches between these two energy storage capacitors to estimate ambient power. Using these estimations, BIONIC can predict and track charging times (i.e., off-time durations) to schedule time-sensitive tasks and complete them on time. Our evaluations showed that BIONIC significantly extends the measurable off-time intervals by a factor of 15 to 1620 compared to state-of-the-art, while achieving an accuracy of up to 99.1% and effectively adapting to new energy conditions. Besides, in a typical batteryless application, BIONIC's power-aware intermittent computing runtime boosted the number of completed time-sensitive operations by 30% while reducing failed timely operations by 29%.

Many embedded applications have strict energy, memory, and time constraints, making neural network (NN) inference particularly challenging. Recently, a novel NN architecture, called Fast Feedforward Networks (FFFs), has been proposed to achieve inference with extremely lightweight computational demands and minimal latency. Yet, compared to feedforward networks with similar sizes, FFFs still lag behind in terms of performance, indicating that they do not utilize all of their parameters effectively. In this article, we explore a possible reason for this performance gap: the uncertainty in how samples are assigned to the network’s leaves. We attempt to overcome this challenge by making FFFs’ training inference-aware, hence introducing Inference-Aware Fast Feedforward Networks (IAFFFs). We imitate FFFs’ inference during training by using a step activation function alongside the traditional sigmoid activation function. We test different aware scheduling methods, which we dub “awareness scheduler”, to adjust the balance between the two activation functions during training, and examine how different schedules impact the model’s performance. Additionally, we employ leaf-weight virtualization with inference-aware retraining to compress our models so they can fit onto edge devices. We further employ an iterative compression approach to find an optimal awareness scheduler for compression to minimize performance drop due to compression. We experiment with different model sizes on various microcontrollers (MCUs) with different memory constraints to observe the latency and energy consumption introduced by the compression algorithm.

Tiny battery-free devices running deep neural networks (DNNs) embody intermittent TinyML, a paradigm at the intersection of intermittent computing and deep learning, bringing sustainable intelligence to the extreme edge. This paper, as an overview of a special session at Embedded Systems Week (ESWEEK) 2025, presents four tales from diverse research backgrounds, sharing experiences in addressing unique challenges of efficient and reliable DNN inference despite the intermittent nature of ambient power. The first explores enhancing inference engines for efficient progress accumulation in hardware-accelerated intermittent inference and designing networks tailored for such execution. The second investigates computationally light, adaptive algorithms for faster, energy-efficient inference, and emerging computing-in-memory architectures for power failure resiliency. The third addresses battery-free networking, focusing on timely neighbor discovery and maintaining synchronization despite spatio-temporal energy dynamics across nodes. The fourth leverages modern nonvolatile memory fault behavior and DNN robustness to save energy without significant accuracy loss, with applicability to intermittent inference on nano-satellites. Collectively, these early efforts advance intermittent TinyML research and promote future cross-domain collaboration to tackle open challenges.

Computing In-Memory (CIM) with emerging nonvolatile memory (NVM) technologies is promising for batteryless systems since it removes the need for explicit backup and energy-hungry data transfer between the processor and memory. However, existing CIM solutions are not effective in accelerating memory-bound inference tasks efficiently on batteryless systems. They operate at relatively low frequencies, complicate application development, and do not consider energy harvesting dynamics to optimize their throughput. To address the issues, this article presents a novel CIM-based batteryless computing platform, called Viadotto, that provides efficient and adaptive acceleration for memory-bound computing workloads. Viadotto meets adaptive CIM and microcontroller-based (MCU-based) conventional batteryless platforms for the first time. Basically, Viadotto exposes a programming model supported by its compiler and a pipelined memory controller, which hides low-level CIM operations from applications. Furthermore, its runtime issues CIM operations in an energy-efficient manner and optimizes throughput in a programmer-transparent way by adapting CIM parallelism to react to ambient power dynamics. Our evaluation shows that Viadotto outperforms existing CIM solutions for batteryless systems by 48%.

Battery-free devices collect the harvested ambient energy in their energy storage capacitors. The size of the storage capacitor is one of the main factors affecting the device’s active time and power failure rate. In fact, a larger capacitor ensures energy autonomy for longer operations, while a smaller capacitor charges faster and shrinks inefficient cold starts. This paper presents CapDYN , a new energy storage architecture that can self-adapt its capacity based on incoming ambient energy. CapDYN automatically reconfigures the size of its capacitor bank to both speed up charging and improve execution rate. CapDYN reduces the startup time by up to 98% and can schedule tasks up to 38% faster, compared to a fixed-size capacitor. CapDYN operates in a fully autonomous manner consuming down to 11.6 µW in its simplest implementation and replaces the power-hungry microcontroller governing the switching operation with a dedicated ultra-low-power circuit built with COTS components. Its power consumption improves the previous state of the art by 73%, all the while featuring uncompromising reactivity. CapDYN can instantly react to sudden power transients without incurring extra power draw by foregoing MCU-driven reconfiguration used in state-of-the-art dynamic energy storages.

Continuous health monitoring is crucial to ensuring better health and taking preventive measures just-in-time. Existing battery-powered health wearables pose a significant limitation to continuous monitoring as batteries wear out after fixed energy cycles and need replacement. Ambient energy harvesting unlocks battery-free sensing but it suffers from spatio-temporal variability, making it unfit for health sensing. Intra-body power transfer (IBPT) provides an alternative energy source for battery-free operation, however, it can only provide limited energy in order to ensure wearer's safety. Existing system support is designed to maximize computational progress in a single energy cycle, thus wasting energy on computations that become stale in the next energy cycle. We instantiate an IBPT-powered health wearable capable of supporting multiple health sensors. To cope with lower incoming energy, we introduce BodyOS; a system support that exposes programming constructs for domain experts to express health applications in terms of the inherent dependencies of bio-signals being monitored by the application. By avoiding unnecessary sensing operations, BodyOS allows energy-efficient application execution and faster capacitor recharge while ensuring that the data sensed by the application is always useful. We evaluate BodyOS to show that it significantly improves energy efficiency, thus increasing the on-time and number of data points collected by the device.

Batteryless energy harvesting devices compute intermittently due to power failures that frequently interrupt the computational activity and lead to charging delays. To ensure functional correctness in intermittent computing, applications must exhibit several unique properties, such as guarantees for computational progress despite power failures and prevention of stale operations caused by charging delays. We observe that current software support for intermittent computing allows for checking only a fixed set of properties and leads to tightly coupled application and property-checking, thus hampering modularity, scalability, and maintainability.

Batteryless edge devices are extremely resource-constrained compared to traditional mobile platforms. Existing tiny deep neural network (DNN) inference solutions are problematic due to their slow and resource-intensive nature, rendering them unsuitable for batteryless edge devices. To address this problem, we propose a new approach to embedded intelligence, called Fast-Inf, which achieves extremely lightweight computation and minimal latency. Fast-Inf uses binary tree-based neural networks that are ultra-fast and energy-efficient due to their logarithmic time complexity. Additionally, Fast-Inf models can skip the leaf nodes when necessary, further minimizing latency without requiring any modifications to the model or retraining. Moreover, Fast-Inf models have significantly lower backup and runtime memory overhead. Our experiments on an MSP430FR5994 platform showed that Fast-Inf can achieve ultra-fast and energy-efficient inference (up to 700x speedup and reduced energy) compared to a conventional DNN.

Processing In-Memory (PIM) based on emerging non-volatile memory technologies can accelerate machine learning tasks even for batteryless devices operating intermittently. However, existing PIM solutions for intermittent systems offer limited parallelism and do not support a high degree of programmability. This paper presents LUTIC —a novel architecture that can accelerate a broader class of intermittent data-intense operations. Our results demonstrate that, compared to existing commercial low-energy accelerators and PIM solutions for intermittent computing, LUTIC improves performance and energy efficiency with better parallelism support.

Task-based intermittent software systems always re-execute peripheral input/output (I/O) operations upon power failures since tasks have all-or-nothing semantics. Re-executed I/O wastes significant time and energy and risks memory inconsistency. This paper presents EaseIO, a new task-based intermittent system that remedies these problems. EaseIO programming interface introduces re-execution semantics for I/O operations to facilitate safe and efficient I/O management for intermittent applications. EaseIO compiler front-end considers the programmer-annotated I/O re-execution semantics to preserve the task's energy efficiency and idem-potency. EaseIO runtime introduces regional privatization to eliminate memory inconsistency caused by idempotence bugs. Our evaluation shows that EaseIO reduces the wasted useful I/O work by up to 3× and total execution time by up to 44% by avoiding 76% of the redundant I/O operations, as compared to the state-of-the-art approaches for intermittent computing. Moreover, for the first time, EaseIO ensures memory consistency during DMA-based I/O operations.

With the progress in energy harvesting circuits and the decrease in power requirements of processing, sensing, and communication hardware, we have the potential of freeing the Internet of Things devices from their batteries. However, removing batteries introduces frequent power failures due to the irregular power availability from the environment. This situation leads devices to compute intermittently under transient environmental power. Intermittent computing requires significant microarchitectural modifications on existing processor designs to ensure automatic computation progress despite the power failures. For example, built-in nonvolatile memory components should be integrated in processor architectures. Consequently, different microarchitectural automatic backup strategies need to be implemented. In this work, we introduce different processor state backup strategies based on an interrupt-based software approach, which do not need modifications to the microarchitecture of existing processors. Therefore, we present a systematic approach to emulate different processor architectures with varying backup strategies under transient power. To justify our claims, we make Ibex RISC-V core, a popular ultralow-power processor architecture, suitable for intermittent computing. This is the first attempt to make a variety of existing and future ultralow-power processor architectures easily exploitable for transiently powered computing systems.

Backing up the intermediate results of hardware-accelerated deep inference is crucial to ensure the progress of execution on batteryless computing platforms. However, hardware accelerators in low-power AI platforms only support the one-shot atomic execution of one neural network inference without any backups. This article introduces a new toolchain for MAX78000, which is a brand-new microcontroller with a hardware-based convolutional neural network (CNN) accelerator. Our toolchain converts any MAX78000-compatible neural network into an intermittently executable form. The toolchain enables finer checkpoint granularity on the MAX78000 CNN accelerator, allowing for backups of any intermediate neural network layer output. Based on the layer-by-layer CNN execution, we propose a new backup technique that performs only necessary (urgent) checkpoints. The method involves the batteryless system switching to ultra-low-power mode while charging, saving intermediate results only when input power is lower than ultra-low-power mode energy consumption. By avoiding unnecessary memory transfer, the proposed solution increases the inference throughput by 1.9× for simulation and by 1.2× for real-world setup compared to the coarse-grained baseline execution.

Energy harvesting battery-free embedded devices rely only on ambient energy harvesting that enables stand-alone and sustainable IoT applications. These devices execute programs when the harvested ambient energy in their energy reservoir is sufficient to operate and stop execution abruptly (and start charging) otherwise. These intermittent programs have varying timing behavior under different energy conditions, hardware configurations, and program structures. This article presents Energy-aware Timing Analysis of intermittent Programs (ETAP), a probabilistic symbolic execution approach that analyzes the timing and energy behavior of intermittent programs at compile time. ETAP symbolically executes the given program while taking time and energy cost models for ambient energy and dynamic energy consumption into account. We evaluate ETAP by comparing the compile-time analysis results of our benchmark codes and real-world application with the results of their executions on real hardware. Our evaluation shows that ETAP’s prediction error rate is between 0.0076% and 10.8%, and it speeds up the timing analysis by at least two orders of magnitude compared to manual testing.

Recent engineering efforts gave rise to the emergence of devices that operate only by harvesting power from ambient energy sources, such as radiofrequency and solar energy. Due to the sporadic ambient energy sources, frequent power failures are inevitable for these devices that rely only on energy harvesting. These devices lose the values maintained in volatile hardware state elements upon a power failure. This situation leads to intermittent execution, which prevents the forward progress of computing operations. To countermeasure power failures, these devices require non-volatile memory elements, e.g., FRAM, to store the computational state. However, hardware designers can only represent volatile state elements using FPGAs in the market and current hardware description languages. As of now, there is no existing solution to fast-prototype non-volatile digital logic. This paper enables FPGA-based emulation of any custom non-volatile digital logic for intermittent computing. Therefore, our proposal can be a standard part of the current FPGA libraries provided by the vendors to design and validate future non-volatile logic designs targeting intermittent computing.

Energy-harvesting IoT devices that operate without batteries paved the way for sustainable sensing applications. These devices force applications to run intermittently since the ambient energy is sporadic, leading to frequent power failures. Unexpected power failures introduce several challenges to wireless communication since nodes are not synchronized and stop operating during data transmission. This paper presents a novel self-powered autonomous circuit design to remedy this problem. This circuit uses visible-light communication (VLC) to enable synchronization for time-slotted energy-aware transiently powered communication. Therefore, it aligns the activity phases of the batteryless sensors so that energy status communication occurs when these nodes are active simultaneously. Evaluations showed that our circuit has an ultra-low power consumption, can work with zero energy cost by relying only on the harvested energy, and supports efficient intermittent communication over intermittently powered nodes.

Battery-free and intermittently powered devices offer long lifetimes and enable deployment in new applications and environments. Unfortunately, developing sophisticated inference-capable applications is still challenging due to the lack of platform support for more advanced (32-bit) microprocessors and specialized accelerators---which can execute data-intensive machine learning tasks, but add complexity across the stack when dealing with intermittent power. We present Protean to bridge the platform gap for inference-capable battery-free sensors. Designed for runtime scalability, meeting the dynamic range of energy harvesters with matching heterogeneous processing elements like neural network accelerators. We develop a modular "plug-and-play" hardware platform, SuperSensor, with a reconfigurable energy storage circuit that powers a 32-bit ARM-based microcontroller with a convolutional neural network accelerator. An adaptive task-based runtime system, Chameleon, provides intermittency-proof execution of machine learning tasks across heterogeneous processing elements. The runtime automatically scales and dispatches these tasks based on incoming energy, current state, and programmer annotations. A code generator, Metamorph, automates conversion of ML models to intermittent safe execution across heterogeneous compute elements. We evaluate Protean with audio and image workloads and demonstrate up to 666x improvement in inference energy efficiency by enabling usage of modern computational elements within intermittent computing. Further, Protean provides up to 166% higher throughput compared to non-adaptive baselines.

Intermittent computing requires custom programming models to ensure the correct execution of applications despite power failures. However, existing programming models lead to the programs that are hardware dependent and not reusable. This article aims at virtualizing intermittent computing to remedy these problems. We introduce PureVM, a virtual machine that abstracts a transiently powered computer, and PureLANG, a continuation-passing-style programming language to develop programs that run on PureVM. This virtualization, for the first time, paves the way for portable and reusable transiently powered applications.

Today’s intermittent computing systems operate by relying only on harvested energy accumulated in their tiny energy reservoirs, typically capacitors. An intermittent device dies due to a power failure when there is no energy in its capacitor and boots again when the harvested energy is sufficient to power its hardware components. Power failures prevent the forward progress of computation due to the frequent loss of computational state. To remedy this problem, intermittent computing systems comprise built-in fast non-volatile memories with high write endurance to store information that persists despite frequent power failures. However, the lack of design tools makes fast-prototyping these systems difficult. Even though FPGAs are common platforms for fast prototyping and behavioral verification of continuously powered architectures, they do not target prototyping intermittent computing systems. This article introduces a new FPGA-based framework, named NORM ( N on-volatile mem OR y e M ulator), to emulate and verify the behavior of any intermittent computing system that exploits fast non-volatile memories. Our evaluation showed that NORM can be used to emulate and validate FeRAM-based transiently powered hardware architectures successfully.

Batteryless devices harvest energy from sporadic ambient sources, enabling a wide range of long-lived, stand-alone, and environmentally-friendly sustainable applications. Software on these devices operates intermittently due to frequent power failures. Each power failure leads the device to lose its computational state that hinders the forward progress of computation and memory consistency. One solution to remedy this situation is to pair programs with checkpoints to save a snapshot of the intermediate program state to non-volatile memory before a power loss. Due to the lack of protection mechanisms in the state-of-the-art intermittent systems, checkpoints can be altered either by programmer errors or deliberately by an attacker. This situation leads to catastrophic effects since the program execution might be corrupted, and in turn, the device might malfunction. In this paper, we propose MPI, a memory protection mechanism for intermittent computing systems. In particular, MPI is a minimal intermittent-compliant trusted computing base acting as a hypervisor that fully manages and protects the underlying memory of a batteryless device. MPI enables a reliable and secure generation and restoration of checkpoints, maintaining their integrity and access control in the presence of remote software-based attacks without trusting the user program or requiring programmer intervention. Notable is that MPI neither requires hardware modifications nor depends on hardware features that might not exist in all batteryless platforms. Our experiments on a real batteryless platform show that MPI provides stronger security guarantees compared to the state-of-the-art approaches, with a comparable time and energy overhead.

Reliable communication and synchronization for transiently-powered batteryless sensors are still open challenges. This paper presents a method to synchronize and ensure reliable communication over batteryless sensors with zero energy cost requirements. Our preliminary design combines visible light communication (VLC) and radio-frequency (RF) backscatter into a self-powered autonomous circuit. We enable energy status sharing and communication scheduling services, which provide the fundamental building blocks for future batteryless communication protocols.

In this study, we propose SQUID, a software-based solution to predict the off-time of batteryless devices that operate in environments with short-term energy-harvesting stability. The key insight of SQUID is to sample the power in the environment when the device is on and use these samples to extrapolate the power availability when the device is off and charging its capacitor. Therefore, SQUID can predict the charging time of the batteryless sensors by using the predicted power availability. Our initial experiments showed that SQUID has a promising estimation accuracy by consuming up to 10 times less energy than existing timekeeping solutions.

Tiny energy harvesting sensors that operate intermittently, without batteries, have become an increasingly appealing way to gather data in hard to reach places at low cost. Frequent power failures make forward progress, data preservation and consistency, and timely operation challenging. Unfortunately, state-of-the-art systems ask the programmer to solve these challenges, and have high memory overhead, lack critical programming features like pointers and recursion, and are only dimly aware of the passing of time and its effect on application quality. We present Time-sensitive Intermittent Computing System (TICS), a new platform for intermittent computing, which provides simple programming abstractions for handling the passing of time through intermittent failures, and uses this to make decisions about when data can be used or thrown away. Moreover, TICS provides predictable checkpoint sizes by keeping checkpoint and restore times small and reduces the cognitive burden of rewriting embedded code for intermittency without limiting expressibility or language functionality, enabling numerous existing embedded applications to run intermittently.

Energy-harvesting devices have enabled Internet of Things applications that were impossible before. One core challenge of batteryless sensors that operate intermittently is reliable timekeeping. State-of-the-art low-power real-time clocks suffer from long start-up times (order of seconds) and have low timekeeping granularity (tens of milliseconds at best), often not matching timing requirements of devices that experience numerous power outages per second. Our key insight is that time can be inferred by measuring alternative physical phenomena, like the discharge of a simple RC circuit, and that timekeeping energy cost and accuracy can be modulated depending on the run-time requirements. We achieve these goals with a multi-tier timekeeping architecture, named Cascaded Hierarchical Remanence Timekeeper (CHRT), featuring an array of different RC circuits to be used for dynamic timekeeping requirements. The CHRT and its accompanying software interface are embedded into a fresh batteryless wireless sensing platform, called Botoks, capable of tracking time across power failures. Low start-up time (max 5 ms), high resolution (up to 1 ms) and run-time reconfigurability are the key features of our timekeeping platform. We developed two time-sensitive batteryless applications to demonstrate the approach: a bicycle analytics tool, where the CHRT is used to track time between revolutions of a bicycle wheel, and wireless communication, where the CHRT enables radio synchronization between two intermittently-powered sensors.

Batteryless embedded devices rely only on ambient energy harvesting that enables stand-alone and sustainable applications for the Internet of Things. These devices perform computation, sensing, and communication when the harvested ambient energy in their energy reservoir is sufficient; they die abruptly when the energy drains out completely. This kind of operation, the so-called intermittent execution, dictates a task-based programming model for the development and implementation of intermittent applications. However, today's task-based intermittent programs are tightly-coupled to the underlying run-time environments. This makes their debugging and testing difficult before deploying them into the target platform. To remedy this, we present Taskify, a tool that enables engineers to write and debug task-based intermittent programs in TaskDSL, i.e., a domain-specific language we designed for the development of intermittent programs on any general-purpose computer. Taskify automatically transforms these programs into C programs that can be linked to the underlying run-time environment and deployed into the target platform. Taskify is implemented as an Eclipse plugin. It has been evaluated on three intermittent applications.

Energy-neutral Internet of Things requires freeing embedded devices from batteries and powering them from ambient energy. Ambient energy is, however, unpredictable and can only power a device intermittently. Therefore, the paradigm of intermittent execution is to save the program state into non-volatile memory frequently to preserve the execution progress. In task-based intermittent programming, the state is saved at task transition. Tasks are fixed at compile time and agnostic to energy conditions. Thus, the state may be saved either more often than necessary or not often enough for the program to progress and terminate. To address these challenges, we propose Coala, an adaptive and efficient task-based execution model. Coala progresses on a multi-task scale when energy permits and preserves the computation progress on a sub-task scale if necessary. Coala’s specialized memory virtualization mechanism ensures that power failures do not leave the program state in non-volatile memory inconsistent. Our evaluation on a real energy-harvesting platform not only shows that Coala reduces runtime by up to 54% as compared to a state-of-the-art system, but also it is able to progress where static systems fail.

Distributed and collaborative computation has never been considered before in networks of batteryless sensors. This can bring many advantages for applications (e.g. longer transmission ranges, lower network costs), however introducing new research challenges. In this paper, we focus on the well-known distributed sensor fusion but in an intermittently-powered batteryless sensor network. The goal is to estimate a parameter collaboratively by considering individual sensor measurements. We show that, even though the nodes stop operation with high probability due to random power failures and they neither communicate with their neighbors nor perform computation most of the time, the simplest implementation of the fully-distributed sensor fusion based on average consensus improves the overall estimation quality of the network considerably. In the light of this, we anticipate that if harvested energy is used efficiently so that nodes have more opportunity to receive and send packets, existing fully-distributed protocols can be implemented with tiny modifications in networks of batteryless sensors.

We characterize the performance of a backscatter tag-to-tag (T2T) multi-hop network. For this, we developed a discrete component-based backscatter T2T transceiver and a communication protocol suite. The protocol composed of a novel (i) flooding-based link control tailored towards backscatter transmission, and (ii) low-power listening MAC. The MAC design is based on the new insight that backscatter reception is more energy costly than transmission. Our experiments show that multi-hopping extends the coverage of backscatter networks by enabling longer backward T2T links (tag far from the exciter sending to the tag close to the exciter). Four hops, for example, extend the communication range by a factor of two. Furthermore, we show that dead spots in multi-hop T2T networks are far less significant than those in the single-hop T2T networks.

Wireless power transfer networks (WPTNs) are composed of dedicated energy transmitters (ETs) that charge energy receivers (ERs) via radio frequency waves. A safe-charging WPTN should keep electromagnetic radiation below predetermined limits meanwhile maximizing the transmitted power. In this paper, we consider this requirement as an optimization problem: the maximization of harvested power by ERs subject to the electro-magnetic safety constraints. In order to provide an approximated solution to this problem, we introduce a dual ascent-like distributed charging algorithm that enables ETs to work without global information and satisfy safety constraints asymptotically. We provide an in-depth theoretical analysis of our algorithm which is supported by numerical simulations.

Battery-free computational RFID platforms, such as WISP (Wireless Identification and Sensing Platform), are intermittently-powered devices designed for replacing existing sensor networks. Accordingly, synchronization appears as one of the crucial building blocks for collaborative and coordinated actions in these platforms. However, intermittent power leads to frequent loss of computational state and short-term clock frequency instability that makes synchronization challenging. In this article, we introduce the WISP-Sync protocol that provides synchronization among WISP tags in the communication range of an RFID reader. WISP-Sync overcomes the aforementioned challenges by employing a Proportional-Integral (PI) controller-inspired algorithm which (i) is adaptive-reactive to short-term clock instabilities; (ii) requires only a few computation steps-suitable for limited harvested energy; and (iii) keeps a few variables to hold the synchronization state-minimum overhead to recover from power interrupts. Evaluations in our testbed showed that WISP-Sync ensured an average synchronization error of approximately 1 ms among the tags with an average energy overhead of 1.85 μJ per synchronization round.

Tiny energy harvesting battery-free devices promise maintenance free operation for decades, providing swarm scale intelligence in applications from healthcare to building monitoring. These devices operate intermittently because of unpredictable, dynamic energy harvesting environments, failing when energy is scarce. Despite this dynamic operation, current programming models are static; they ignore the event-driven and time-sensitive nature of sensing applications, focusing only on preserving forward progress while maintaining performance. This paper proposes InK; the first reactive kernel that provides a novel way to program these tiny energy harvesting devices that focuses on their main application of event-driven sensing. InK brings an event-driven paradigm shift for batteryless applications, introducing building blocks and abstractions that enable reacting to changes in available energy and variations in sensing data, alongside task scheduling, while maintaining a consistent memory and sense of time. We implemented several event-driven applications for InK, conducted a user study, and benchmarked InK against the state-of-the-art; InK provides up to 14 times more responsiveness and was easier to use. We show that InK enables never before seen batteryless applications, and facilitates more sophisticated batteryless programs.

The accurate and efficient operation of many applications and protocols in wireless sensor networks require synchronized notion of time. To achieve network-wide time synchronization, a common strategy is to flood current time information of a reference node into the network, which is utilized by the de facto time-synchronization protocol Flooding Time-Synchronization Protocol (FTSP). In FTSP, the propagation speed of the flood is slow because each node waits for a given period of time to propagate its time information about the reference node. It has been shown that slow-flooding decreases the synchronization accuracy and scalability of FTSP drastically. Alternatively, rapid-flooding approach is proposed in the literature, which allows nodes to propagate time information as quickly as possible. However, rapid flooding is difficult and has several drawbacks in wireless sensor networks. In this paper, our aim is to reduce the undesired effect of slow-flooding on the synchronization accuracy without changing the propagation speed of the flood. Within this context, we realize that the smaller the difference between the speeds of the clocks, the smaller the undesired effect of waiting times on the synchronization accuracy. In the light of this realization, our main contribution is to show that the synchronization accuracy and scalability of slow-flooding can drastically be improved by employing a clock speed agreement algorithm among the sensor nodes. We present an evaluation of this strategy on a testbed setup including 20 MICAz sensor nodes. Our theoretical findings and experimental results show that employing a clock speed agreement algorithm among the sensor nodes drastically improves the synchronization accuracy and scalability of slow-flooding.

Synchronization to an external time source such as Coordinated Universal Time (UTC), i.e., external synchronization, while preserving tight synchronization among neighboring sensor nodes may be crucial for applications such as determining the speed of a moving object in wireless sensor networks. However, existing time synchronization protocols in the literature, which can be used for external synchronization, poorly synchronize neighboring nodes. On the other hand, the only protocol that aims at optimizing the synchronization error between neighboring nodes is lack of a mechanism which synchronizes sensor nodes to a reference node, and hence, it cannot provide external synchronization. Therefore, there is a lack in the literature of a time synchronization protocol, which can be used by applications demanding both external synchronization and tight synchronization among neighboring nodes. In this paper, we answer the question of whether it is possible for sensor nodes to synchronize to a reference node while they optimize the clock skew between their neighboring nodes at the same time. Within this context, we present a novel time synchronization protocol, namely External Gradient Time Synchronization Protocol (EGSync). In EGSync, each sensor node synchronizes to a reference node by using time information flooded by this node, as well as synchronizes to its neighboring nodes by employing the agreement algorithm. We implemented EGSync on the MICAz platform using TinyOS and evaluated it on a testbed setup including 20 sensor nodes. We present the experimental results on our testbed and the simulation results for networks with larger diameters and densities.

A desirable flooding-based time synchronization protocol in Wireless Sensor Networks (WSNs) should neither demand fast propagation of up-to-date time information nor keeping track of the neighboring nodes. Moreover, such a protocol is strictly required to have low computational and communication overhead as well as small memory footprint. Would there be a protocol which meets these requirements' We answer this question positively by introducing a novel time synchronization protocol whose main component is “adaptive-value tracking”. Thanks to this component, each sensor node synchronizes the rate of its clock to that of a reference clock through successive feedbacks with a considerably low computational and memory overhead. By adjusting time offset of the rate-synchronized clocks, the network-wide synchronization is established even without demanding rapid propagation of the reference clock and keeping track of the neighboring nodes. In the light of our experimental evaluation in a testbed of 20 MICAz sensor nodes, we observed that the proposed protocol provides similar synchronization under the same communication frequency with an approximately 97% less CPU overhead and 80% less memory allocation compared to the recent flooding based time synchronization protocols in WSNs.