Demo Data from EDBT 2026 / reviewers in the wild / expert
Vlad Gheorghiu
dblp:129/1641
· DBLP profile ↗
4ranked-venue papers
2as first author
2since 2021 · last 2025
0000-0002-4172-9186ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021Security and privacy · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Emerging computing paradigms · 100% | |
| Network and information security
1 paper |
Cryptographic primitives and cryptanalysis · 100% | |
| Theoretical computer science
1 paper |
Quantum computing and quantum information · 100% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Emerging computing paradigms › quantum computer architecture › quantum circuit optimization
CNOT gate reduction |
0.7 | 1 | 2023 | Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Emerging computing paradigms › quantum computer architecture
quantum compilation |
0.7 | 1 | 2023 | Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Emerging computing paradigms
quantum computer architecture |
0.7 | 1 | 2023 | Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Emerging computing paradigms
quantum computing |
0.7 | 1 | 2023 | Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Emerging computing paradigms › quantum computer architecture
qubit connectivity |
0.7 | 1 | 2023 | Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Cryptographic primitives and cryptanalysis › post-quantum cryptography
lattice-based cryptography |
0.4 | 1 | 2020 | Estimating Quantum Speedups for Lattice Sieves · ASIACRYPT (2) 2020 |
Cryptographic primitives and cryptanalysis › post-quantum cryptography › lattice-based cryptography › shortest vector problem
lattice sieving |
0.4 | 1 | 2020 | Estimating Quantum Speedups for Lattice Sieves · ASIACRYPT (2) 2020 |
Cryptographic primitives and cryptanalysis
post-quantum cryptography |
0.4 | 1 | 2020 | Estimating Quantum Speedups for Lattice Sieves · ASIACRYPT (2) 2020 |
Quantum computing and quantum information
quantum algorithms |
0.4 | 1 | 2020 | Estimating Quantum Speedups for Lattice Sieves · ASIACRYPT (2) 2020 |
Methods — techniques the papers use, named apart from their topics
steiner tree · 0.7circuit slicing · 0.7quantum walks · 0.4quantum walk · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Quantum resource estimation for large scale quantum algorithmsabstractQuantum algorithms are often represented in terms of quantum circuits operating on ideal (logical) qubits. However, the practical implementation of these algorithms poses significant challenges. Many quantum algorithms require a substantial number of logical qubits, and the inherent susceptibility to errors of quantum computers require quantum error correction. The integration of error correction introduces overhead in terms of both space (physical qubits required) and runtime (how long the algorithm needs to be run for). This paper addresses the complexity of comparing classical and quantum algorithms, primarily stemming from the additional quantum error correction overhead. We propose a comprehensive framework that facilitates a direct and meaningful comparison between classical and quantum algorithms. By acknowledging and addressing the challenges introduced by quantum error correction, our framework aims to provide a clearer understanding of the comparative performance of classical and quantum computing approaches. This work contributes to understanding the practical viability and potential advantages of quantum algorithms in real-world applications. We apply our framework to quantum cryptanalysis, since it is well known that quantum algorithms can break factoring and discrete logarithm based cryptography and weaken symmetric cryptography and hash functions. In order to estimate the real-world impact of these attacks, apart from tracking the development of fault-tolerant quantum computers it is important to have an estimate of the resources needed to implement these quantum attacks. This analysis provides state-of-the art snap-shot estimates of the realistic costs of implementing quantum attacks on these important cryptographic algorithms, assuming quantum fault-tolerance is achieved using surface code methods, and spanning a range of potential error rates. These estimates serve as a guide for gauging the realistic impact of these algorithms and for benchmarking the impact of future advances in quantum algorithms, circuit synthesis and optimization, fault-tolerance methods and physical error rates. Vlad Gheorghiu, Michele Mosca |
Future Gener. Comput. Syst. | 1 |
| 2023 | Reducing the CNOT Count for Clifford+T Circuits on NISQ ArchitecturesabstractWhile mapping a quantum circuit to the physical layer one has to consider the numerous constraints imposed by the underlying hardware architecture. Connectivity of the physical qubits is one such constraint that restricts two-qubit operations, such as CNOT, to “connected” qubits. SWAP gates can be used to place the logical qubits on admissible physical qubits, but they entail a significant increase in CNOT-count. In this article, we consider the problem of reducing the CNOT-count in Clifford+T circuits on connectivity-constrained architectures, like noisy intermediate-scale quantum (NISQ) computing devices. We “slice” the circuit at the position of Hadamard gates and “build” the intermediate$\{\text {CNOT},{T}\}$subcircuits using Steiner trees, significantly improving on previous methods. We compared the performance of our algorithms while mapping different benchmark and random circuits to some well-known architectures, such as 9-qubit square grid, 16-qubit square grid, Rigetti 16-qubit Aspen, 16-qubit IBM QX5, and 20-qubit IBM Tokyo. Our methods give less CNOT-count compared to Qiskit and TKET transpiler as well as using SWAP gates. Assuming most of the errors in an NISQ circuit implementation are due to CNOT errors, then our method would allow circuits with a few times more CNOT gates be reliably implemented than the previous methods would permit. Vlad Gheorghiu, Jiaxin Huang 0011, Sarah Meng Li, Michele Mosca, Priyanka Mukhopadhyay |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2020 | Estimating Quantum Speedups for Lattice Sieves
Martin R. Albrecht, Vlad Gheorghiu, Eamonn W. Postlethwaite, John M. Schanck |
ASIACRYPT (2) | 2 |
| 2016 | Estimating the Cost of Generic Quantum Pre-image Attacks on SHA-2 and SHA-3
Matthew Amy, Olivia Di Matteo, Vlad Gheorghiu, Michele Mosca, Alex Parent, John M. Schanck |
SAC | 3 |