Demo Data from EDBT 2026 / reviewers in the wild / expert
Toshiya Kotani
dblp:129/1987
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% | |
| Artificial intelligence
1 paper |
Learning theory · 100% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
lithography |
0.3 | 1 | 2018 | Subresolution Assist Feature Generation With Supervised Data Learning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › physical design
mask optimization |
0.3 | 1 | 2018 | Subresolution Assist Feature Generation With Supervised Data Learning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › semiconductor manufacturing
resolution enhancement techniques |
0.3 | 1 | 2018 | Subresolution Assist Feature Generation With Supervised Data Learning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › physical design › optical proximity correction
subresolution assist feature generation |
0.3 | 1 | 2018 | Subresolution Assist Feature Generation With Supervised Data Learning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › physical design › routing › detailed routing
grid routing |
0.2 | 1 | 2015 | Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Electronic design automation › physical design › lithography
multiple patterning lithography |
0.2 | 1 | 2015 | Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Electronic design automation
physical design |
0.2 | 1 | 2015 | Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Electronic design automation › physical design
routing |
0.2 | 1 | 2015 | Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015 |
Machine learning › Learning theory › classification
supervised classification |
0.1 | 1 | 2018 | Subresolution Assist Feature Generation With Supervised Data Learning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Methods — techniques the papers use, named apart from their topics
support vector machine · 0.7logistic regression · 0.7feature extraction · 0.7graph coloring · 0.2dummy pattern flipping · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Subresolution Assist Feature Generation With Supervised Data LearningabstractSubresolution assist feature (SRAF) generation is a very important resolution enhancement technique to improve yield in modern semiconductor manufacturing process. Model-based and rule-based approaches are widely adopted in the semiconductor industry. The model-based SRAF generation can achieve a high accuracy but it is known to be time-consuming and it is hard to obtain consistent SRAFs on the same layout pattern configurations. The rule-based SRAF generation is highly technology dependent and it is becoming extremely difficult to render high-quality results in advanced technology nodes. This paper proposes supervised data learning techniques for fast yet consistent SRAF generation with high-quality results. We first propose the constrained concentric circle with area sampling scheme for feature extraction. Illumination source symmetry-based feature compaction technique is further invented to reduce the training data set size and achieve consistent SRAF predictions. Using accurate model-based SRAFs as training data, classification models based on logistic regression (LGR) and support vector machine are calibrated for SRAF predictions. Moreover, the probability maximum prediction is proposed to generate manufacturing-friendly SRAFs with a greedy simplification scheme. We compare support vector machine and LGR models by embedding into an entire mask optimization flow, where the support vector machine model obtains better lithographic performance. Experimental results demonstrate that, compared with the commercial Calibre tool, supervised data learning techniques for SRAF generation obtain significant speed up (>3X for a 100 um2layout clip) and comparable lithographic performance in terms of edge placement error and process variation band. Yibo Lin, Meng Li 0004, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 7 |
| 2016 | A Machine Learning Based Framework for Sub-Resolution Assist Feature GenerationabstractSub-Resolution Assist Feature (SRAF) generation is a very important resolution enhancement technique to improve yield in modern semiconductor manufacturing process. Model- based SRAF generation has been widely used to achieve high accuracy but it is known to be time consuming and it is hard to obtain consistent SRAFs on the same layout pattern configurations. This paper proposes the first ma- chine learning based framework for fast yet consistent SRAF generation with high quality of results. Our technical con- tributions include robust feature extraction, novel feature compaction, model training for SRAF classification and pre- diction, and the final SRAF generation with consideration of practical mask manufacturing constraints. Experimental re- sults demonstrate that, compared with commercial Calibre tool, our machine learning based SRAF generation obtains 10X speed up and comparable performance in terms of edge placement error (EPE) and process variation (PV) band. Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan |
ISPD | 5 |
| 2015 | Self-Aligned Double and Quadruple Patterning Aware Grid Routing MethodsabstractAlthough self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all layouts are compatible with them. In advanced technologies, feasible wafer image should be generated effectively by utilizing SADP and SAQP where a wafer image is determined by a selected mandrel pattern. However, predicting a mandrel pattern is not easy since it is different from the wafer image (or target pattern). In this paper, we propose new routing methods for spacer-is-dielectric (SID)-type SADP, SID-type SAQP, and spacer-is-metal (SIM)-type SADP to generate a feasible layout satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SID-type SADP) or three colors (SID-type SAQP and SIM-type SADP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, we try to reduce hotspots (potentially defective regions) by the proposed dummy pattern flipping for SID-type SADP. In experiments, feasible layouts meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed. Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Fumiharu Nakajima, Shigeki Nojima, Toshiya Kotani, Takeshi Ihara, Atsushi Takahashi 0001 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 6 |
| 2013 | Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots controlabstractAlthough Self-Aligned Double and Quadruple Patterning (SADP, SAQP) have become the most promising processes for sub-20 nm and sub-14 nm node advanced technologies, not all wafer images are realized by them. In advanced technologies, feasible wafer images should be generated effectively by utilizing SADP and SAQP where a wafer image is uniquely determined by a selected mandrel pattern. However, predicting the wafer image of a mandrel pattern is not easy. In this paper, we propose a routing method of generating a feasible wafer image satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SADP) or three colors (SAQP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, hotspot reduction by dummy pattern flipping is proposed. In experiments, feasible wafer images meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed. Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto, Atsushi Takahashi 0001 |
ASP-DAC | 4 |