Pengcheng Huang 0001

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24ranked-venue papers
7as first author
6since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 16 · 5 first-author · 3 since 2021Applied, interdisciplinary, general and emerging computing · 5 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-author
YearPublicationVenuePosition
2025 Lossless Compression of Time Series Data: A Comparative Study
abstract
Our increasingly digital and connected world has led to the generation of unprecedented amounts of data. This data must be efficiently managed, transmitted, and stored to preserve resources and allow scalability. Data compression has therein been a key technology for a long time, resulting in a vast landscape of available techniques. This largest-to-date study analyzes and compares various lossless data compression methods for time series data. We present a unified framework encompassing two stages: data transformation and entropy encoding. We evaluate compression algorithms across both synthetic and real-world datasets with varying characteristics. Through ablation studies at each compression stage, we isolate the impact of individual components on overall compression performance–revealing the strengths and weaknesses of different algorithms when facing diverse time series properties. Our study underscores the importance of well-configured and complete compression pipelines beyond individual components or algorithms; it offers a comprehensive guide for selecting and composing the most appropriate compression algorithms tailored to specific datasets.
Jonas G. Matt, Pengcheng Huang 0001, Balz Maag
ETFA2
2024 Workshop: Efficient and Effective Multi-Objective AutoML for Industrial Data Analytics
Tanmay Goyal, Pengcheng Huang 0001, Balz Maag
EWSN2
2024 Work in Progress: Early Timing Prediction of Real-Time Tasks in Continuous Integration Environments
abstract
Timing prediction for real-time systems, especially those based on multi-core processor technology, presents enor-mous challenges in the design of modern industrial control sys-tems. Classical timing analysis techniques that have been effective in the past cannot yet keep up with the increased complexity of industrial control systems. Therefore, using hardware-in-the-loop testing to understand the timing behavior of real-time tasks is a prevalent practice across many industries. However, applying this state-of-the-practice to Continuous Integration (CI) software development workflows is expensive, and frequently leads to delayed developer feedback on task timing for code commits. To address this challenge, we propose the Chronos framework, which focuses on improving development efficiency of industrial control system software. Chronos utilizes CI data from both simulation and hardware-in-the-loop testing to build machine learning based, cross-platform timing prediction models, which correlate the simulated performance of the tasks with their actual timing observed on the target embedded hardware. For any new code that is committed, the timing prediction is triggered by the CI server with the trained machine learning models, enabling fast feedback on timing behavior of the committed code. We demonstrate the effectiveness of Chronos with preliminary results on real industrial control system setups.
Pengcheng Huang 0001, Balz Maag, Thanikesavan Sivanthi, Chunwei Xing
RTAS1
2022 SMiLe: Automated End-to-end Sensing and Machine Learning Co-Design
Tanmay Goyal, Pengcheng Huang 0001, Felix Sutton, Balz Maag, Philipp Sommer
EWSN2
2022 Poster: Empirical Evaluation of AutoML Algorithms for Motor Health Prediction
Tanmay Goyal, Pengcheng Huang 0001, Felix Sutton, Balz Maag, Philipp Sommer
EWSN2
2021 Schedulability of probabilistic mixed-criticality systems
abstract
Abstract Mixed-criticality systems often need to fulfill safety standards that dictate different requirements for each criticality level, for example given in the ‘probability of failure per hour’ format. A recent trend suggests designing this kind of systems by jointly scheduling tasks of different criticality levels on a shared platform. When this is done, the usual assumption is that tasks of lower criticality are degraded when a higher criticality task needs more resources, for example when it overruns a bound on its execution time. However, a way to quantify the impact this degradation has on the overall system is not well understood. Meanwhile, to improve schedulability and to avoid over-provisioning of resources due to overly pessimistic worst-case execution time estimates of higher criticality tasks, a new paradigm emerged where task’s execution times are modeled with random variables. In this paper, we analyze a system with probabilistic execution times, and propose metrics that are inspired by safety standards. Among these metrics are the probability of deadline miss per hour, the expected time before degradation happens, and the duration of the degradation. We argue that these quantities provide a holistic view of the system’s operation and schedulability.
Stefan Draskovic, Pengcheng Huang 0001, Lothar Thiele
Real Time Syst.3
2019 FFOB: efficient online mode-switch procrastination in mixed-criticality systems
Biao Hu 0001, Lothar Thiele, Pengcheng Huang 0001, Kai Huang 0001, Christoph Griesbeck, Alois C. Knoll
Real Time Syst.3
2017 Isolation scheduling on multicores: model and scheduling approaches
Georgia Giannopoulou, Pengcheng Huang 0001, Davide B. Bartolini, Lothar Thiele
Real Time Syst.2
2017 On The Design and Application of Thermal Isolation Servers
abstract
Recently, there has been an increasing trend towards executing real-time applications on multi-core platforms. However, this complicates the design problem, as applications running on different cores can interfere due to shared resources and mediums. In this paper, we focus on thermal interference, where a given task (τ 1 ) heats the processor, resulting in reduced service (due to Dynamic Thermal Management (DTM)) to another task (τ 2 ). In real-time domain, where tasks have deadline constraints, thermal interference is a substantial problem as it directly impacts the Worst Case Execution Time (WCET) of the effected application (τ 2 ). The problem exacerbates as we move to mixed-criticality systems, where the criticality of τ 2 may be greater than the criticality of τ 1 , complicating the certification process. In this paper, we propose a server based strategy (Thermal Isolation Server (TI Server)) which can be used to avoid thermal interference of applications. We also present a heuristic to design TI Servers to meet the timing constraints of all tasks and the thermal constraints of the system. TI Servers are time/space composable, and can be applied to a variety of task models. We also evaluate TI Servers on a hardware test-bed for validation purposes.
Pengcheng Huang 0001, Max Millen, Lothar Thiele
ACM Trans. Embed. Comput. Syst.2
2016 Towards the design of fault-tolerant mixed-criticality systems on multicores
abstract
Mixed-criticality is a significant recent trend in the embedded system industry, where common computing platforms are utilized to host functionalities of varying criticality levels. To date, most scheduling techniques have focused on the timing aspect of this problem, while functional safety (i.e. fault-tolerance) is often neglected.
Luyuan Zeng, Pengcheng Huang 0001, Lothar Thiele
CASES2
2016 On-the-fly fast overrun budgeting for mixed-criticality systems
abstract
In mixed-criticality scheduling, the widely assumed mode-switch scheme assumes that both high- and low-criticality tasks are schedulable when no tasks overrun (normal mode) and all high-criticality tasks are schedulable even when they overrun (critical mode, where low-criticality tasks are abandoned/degraded). However, this scheme triggers a mode-switch immediately after any task overruns, which can be abrupt and pessimistic. In this paper, we tackle dual-criticality systems scheduled by earliest-deadline-first, and propose light-weight mode-switch schemes that are effective in keeping the system "away" from the critical mode. Our main idea is to perform overrun budgeting for all tasks as a whole, by monitoring task executions and updating a common overrun budget. This way, the overrun budget is shared among all tasks, and adaptively replenished leveraging run-time information; consequently, mode-switch can be postponed as much as possible. Experimental results demonstrate that the proposed mode-switch schemes outperform existing solutions to a large extent, in reducing the abandoned jobs and mode-switch frequencies, as well as in increasing the time ratio that all tasks are scheduled in the system.
Biao Hu 0001, Kai Huang 0001, Pengcheng Huang 0001, Lothar Thiele, Alois C. Knoll
EMSOFT3
2016 Exploring Energy Saving for Mixed-Criticality Systems on Multi-Cores
abstract
In this paper we study a general energy minimization problem for mixed-criticality systems on multi-cores, considering different system operation modes, and static & dynamic energy consumption. While making global scheduling decisions, trade-offs in energy consumption between different modes and also between static and dynamic energy consumption are required. Thus, such a problem is challenging. To this end, we first develop an optimal solution analytically for unicore and a corresponding low-complexity heuristic. Leveraging this, we further propose energy-aware mapping techniques and explore energy savings for multi-cores. To the best of our knowledge, we are the first to investigate mixed-criticality energy minimization in such a general setting. The effectiveness of our approaches in energy reduction is demonstrated through both extensive simulations and a realistic industrial application.
Sujay Narayana, Pengcheng Huang 0001, Georgia Giannopoulou, Lothar Thiele, R. Venkatesha Prasad
RTAS2
2016 End-to-End Real-Time Guarantees in Wireless Cyber-Physical Systems
abstract
In cyber-physical systems (CPS), the communication among the sensing, actuating, and computing elements is often subject to hard real-time constraints. Real-time communication among wireless network interfaces and real-time scheduling for complex, dynamic applications have been intensively studied. Despite these major efforts, there is still a significant gap to fill. In particular, the integration of several real-time components to provide end-to-end real-time guarantees between interfaces of distributed applications in wireless CPS is an unsolved problem. We thus present a distributed protocol that considers the complete transmission chain including peripheral busses, memory accesses, networking interfaces, and the wireless real-time protocol. Our protocol provably guarantees that message buffers along this chain do not overflow and that all messages received at the destination application interface meet their end-to-end deadlines. To achieve this while being adaptive to unpredictable changes in the system and the real-time traffic requirements, our protocol establishes at run-time a set of contracts among all major elements of the transmission chain based on a worst-case delay and buffer analysis of the overall system. Using simulations, we validate that our analytic bounds are both safe and tight.
Romain Jacob, Marco Zimmerling, Pengcheng Huang 0001, Jan Beutel, Lothar Thiele
RTSS3
2016 Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources
Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang 0001, Lothar Thiele, Benoît Dupont de Dinechin
Real Time Syst.3
2015 Run and be safe: mixed-criticality scheduling with temporary processor speedup
Pengcheng Huang 0001, Georgia Giannopoulou, Lothar Thiele
DATE1
2015 Mixed-criticality runtime mechanisms and evaluation on multicores
abstract
Multicore systems are being increasingly used for embedded system deployments, even in safety-critical domains. Co-hosting applications of different criticality levels in the same platform requires sufficient isolation among them, which has given rise to the mixed-criticality scheduling problem and several recently proposed policies. Such policies typically employ runtime mechanisms to monitor task execution, detect exceptional events like task overruns, and react by switching scheduling mode. Implementing such mechanisms efficiently is crucial for any scheduler to detect runtime events and react in a timely manner, without compromising the system’s safety. This paper investigates implementation alternatives for these mechanisms and empirically evaluates the effect of their runtime overhead on the schedulability of mixed-criticality applications. Specifically, we implement in user-space two state-of-the-art scheduling policies: the flexible time-triggered FTTS [1] and the partitioned EDFVD [2], and measure their runtime overheads on a 60-core Intel R Xeon Phi and a 4-core Intel R Core i5 for the first time. Based on extensive executions of synthetic task sets and an industrial avionic application, we show that these overheads cannot be neglected, esp. on massively multicore architectures, where they can incur a schedulability loss up to 97%. Evaluating runtime mechanisms early in the design phase and integrating their overheads into schedulability analysis seem therefore inevitable steps in the design of mixed-criticality systems. The need for verifiably bounded overheads motivates the development of novel timing-predictable architectures and runtime environments specifically targeted for mixed-criticality applications.
Lukas Sigrist, Georgia Giannopoulou, Pengcheng Huang 0001, Andres Gomez 0001, Lothar Thiele
RTAS3
2015 An Isolation Scheduling Model for Multicores
abstract
Efficiently exploiting multicore processors for real-time applications is challenging because jobs that run concurrently on different cores can interfere on shared resources, severely complicating precise timing analysis. We propose a new scheduling model called Isolation Scheduling (IS), IS provides a framework to exploiting multicores for real-time applications where tasks are grouped in classes. IS enforces mutually exclusive execution among different task classes, thus avoiding inter-class interference by construction. We show that IS encompasses several recent advances in real-time scheduling as special cases and we propose global and partitioned scheduling algorithms based on this model. Specific results are provided if the task classes correspond to different safety criticality levels.
Pengcheng Huang 0001, Georgia Giannopoulou, Davide B. Bartolini, Lothar Thiele
RTSS1
2014 Service adaptions for mixed-criticality systems
abstract
Complex embedded systems are typically mixed-critical, where heterogeneous guarantees must be provided for functionalities of different criticalities. We study in this paper the reconfiguration of services provided to low criticality tasks in reaction to the overruns of high criticality tasks. We further investigate the quantification of the resetting time of the system services. For both service reconfiguration and resetting, we derive tight analysis results under Earliest Deadline First (EDF) scheduling.
Pengcheng Huang 0001, Georgia Giannopoulou, Nikolay Stoimenov, Lothar Thiele
ASP-DAC1
2014 On the Scheduling of Fault-Tolerant Mixed-Criticality Systems
abstract
We consider in this paper fault-tolerant mixed-criticality scheduling, where heterogeneous safety guarantees must be provided to functionalities (tasks) of varying criticalities (importances). We model explicitly the safety requirements for tasks of different criticalities according to safety standards, assuming hardware transient faults. We further provide analysis techniques to bound the effects of task killing and service degradation on the system safety and schedulability. Based on our model and analysis, we show that our problem can be converted to a conventional mixed-criticality scheduling problem. Thus, we broaden the scope of applicability of the conventional mixed-criticality scheduling techniques. Our proposed techniques are validated with a realistic flight management system application and extensive simulations.
Pengcheng Huang 0001, Hoeseok Yang, Lothar Thiele
DAC1
2014 An Efficient Real Time Fault Detection and Tolerance Framework Validated on the Intel SCC Processor
abstract
We present a new framework that efficiently detects and tolerates timing faults in real time systems. Timing faults are observed when the inputs and/or outputs of a given system fail to meet their desired timing properties, such as I/O rates. Most current approaches either rely on heartbeat monitoring which is too restrictive; or on statistical or inexact methods which are not suitable for embedded real time systems. Current approaches based on the abstract real time model of the given application are resource intensive, and may not be suitable for embedded systems. Our framework utilizes active replication, and is based on already existing timing models for real time applications to develop fault detection and tolerance strategies. The approach does not require any timekeeping at runtime, and is efficient in terms of computational resources used. Experiments using three realistic applications on the Intel Baremetal SCC demonstrate the efficiency of our framework, both in memory and computational resources used.
Devendra Rai, Pengcheng Huang 0001, Nikolay Stoimenov, Lothar Thiele
DAC2
2014 Mapping mixed-criticality applications on multi-core architectures
abstract
A common trend in real-time embedded systems is to integrate multiple applications on a single platform. Such systems are known as mixed-criticality (MC) systems when the applications are characterized by different criticality levels. Nowadays, multicore platforms are promoted due to cost and performance benefits. However, certification of multicore MC systems is challenging as concurrently executed applications of different criticalities may block each other when accessing shared platform resources. Most of the existing research on multicore MC scheduling ignores the effects of resource sharing on the response times of applications. Recently, a MC scheduling strategy was proposed, which explicitly accounts for these effects. This paper discusses how to combine this policy with an optimization method for the partitioning of tasks to cores as well as the static mapping of memory blocks, i.e., task data and communication buffers, to the banks of a shared memory architecture. Optimization is performed at design time targeting at minimizing the worst-case response times of tasks and achieving efficient resource utilization. The proposed optimization method is evaluated using an industrial application.
Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang 0001, Lothar Thiele
DATE3
2014 Energy efficient DVFS scheduling for mixed-criticality systems
abstract
Consolidating functionalities with different safety requirements into a common platform gives rise to mixed-criticality systems. The state-of-the-art research has focused on providing heterogeneous timing guarantees for tasks of varying criticality levels. This is achieved by dropping less critical tasks when critical tasks overrun. However, with drastically increased computing requirements and the often battery-operated nature of mixed-criticality systems, energy minimization for such systems is also becoming crucial. In fact, this has already been possible since many modern processors are equipped with the capacity of dynamic voltage and frequency scaling (DVFS), where processor frequency can be reduced at runtime to save energy.
Pengcheng Huang 0001, Georgia Giannopoulou, Lothar Thiele
EMSOFT1
2013 Scheduling of mixed-criticality applications on resource-sharing multicore systems
abstract
A common trend in real-time safety-critical embedded systems is to integrate multiple applications on a single platform. Such systems are known as mixed-criticality (MC) systems as the applications are usually characterized by different criticality levels (CLs). Nowadays, multicore platforms are promoted due to cost and performance benefits. However, certification of multicore MC systems is challenging because concurrently executed applications with different CLs may block each other when accessing shared platform resources. Most of the existing research on multicore MC scheduling ignores the effects of resource sharing on the execution times of applications. This paper proposes a MC scheduling strategy which explicitly accounts for these effects. Applications are executed by a flexible time-triggered criticality-monotonic scheduling scheme. Schedulers on different cores are dynamically synchronized such that only a statically known subset of applications of the same CL can interfere on shared resources, e. g.,memories, buses. Therefore, the timing effects of resource sharing are bounded and we quantify them at design time. We combine this scheduling strategy with a mapping optimization technique for achieving better resource utilization. The efficiency of the approach is demonstrated through extensive simulations as well as comparisons with traditional temporal partitioning and state-of-the-art scheduling algorithms. It is also validated on a real-world avionics system.
Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang 0001, Lothar Thiele
EMSOFT3
2013 Interference Constraint Graph - A new specification for mixed-criticality systems
abstract
Current research in mixed-criticality systems assumes that any task of lower criticality levels can be dropped at anytime in order to guarantee the schedulability of tasks of higher criticality levels. However, in an industrial mixed-criticality system, tasks may interfere with each other only under certain scenarios. Currently a designer does not have any means to specify or control this. The paper proposes the Interference Constraint Graph (ICG) which specifies the allowed interferences between tasks. The new specification formalism generalizes and can easily express many of the existing mixed-criticality scheduling conditions. In spite of its generality, we show that standard fixed-priority scheduling can be efficiently applied. Experiments demonstrate that the ICG model enables systematic reduction of the number of tasks that can be dropped.
Pengcheng Huang 0001, Nikolay Stoimenov, Lothar Thiele
ETFA1