Analog pre-processing has been shown to be energy efficient in a wide variety of low-power applications. Reprogrammable analog devices have leveraged this energy efficiency and applied it to a wider application space, but they still require accurate and stable bias currents for proper operation. For single-application devices, it is sufficient to create temperature compensation schemes that apply to a single bias current. But for reprogrammable or reconfigurable platforms which can be used in a variety of applications, temperature compensation must work well over a large range of potential bias currents and for a large number of different components. In this paper, we present temperature compensation for floating-gate transistors in a reconfigurable system which improves performance over a wide range of currents and temperatures.

Many energy constrained devices such as cell-phones and wearable medical devices utilize sparse or bursty signals — signals characterized by relatively short periods of high activity. Traditional Nyquist-Rate converters are an inefficient tool for converting sparse signals, as a great deal of energy is wasted converting portions of the signal with relatively-low information content. Asynchronous sampling methods attempt to circumvent this inefficiency by sampling based upon the characteristics of the signal itself. However, many asynchronous sampling solutions struggle with a robustness/resolution trade-off. In this paper, we present a new paradigm in which a flexible analog frontend is paired with an asynchronous successive approximation data converter and an asynchronous time-to-digital converter. The result of this paradigm is that the system can be adapted to individual applications, allowing specific data points to be targeted and avoiding data conversion inefficiency. The system will be demonstrated along with the example application of measuring the QRS-complex within an ECG waveform. The demonstrated system, fabricated in standard 0.5μm and 0.35μm processes, produces a minimal number of voltage/time pairs required for studying the QRS complex while consuming 5.96μW of static power.

To meet the demanding requirements in the growing area of wireless sensing applications, some sensing platforms have included low-power application-specific hardware to process the sensor data for compression and pre-classification of the relevant information. While this additional hardware can reduce the overall power consumption of the system, a unique hardware solution is required for each application. To diminish this burden, we will demonstrate a reconfigurable analog/mixed-signal sensing platform. At the hardware-level, this platform consists of a reconfigurable integrated circuit containing many commonly used circuit components that can be connected in any configuration to perform sensor interfacing and ultra-low-power signal processing. At the software level, this platform provides a framework for abstracting the underlying hardware. We will demonstrate how our platform allows a developer to create applications ranging from standard sensor interfacing techniques to more complicated intelligent pre-processing and wake-up detection, without the necessity of circuit-level expertise.

The requirements of many wireless sensing applications approach, or even exceed, the limited hardware capabilities of energy-constrained sensing platforms. To achieve such demanding requirements, some sensing platforms have included low-power application-specific hardware---at the expense of generality---to pre-process the sensor data for reduction to only the relevant information. While this additional hardware can save power by reducing the activity of the microcontroller and radio, a unique hardware solution is required for each application, which presents an unrealistic burden in terms of design time, cost, and ease of integration. To diminish these burdens, we present a reconfigurable analog/mixed-signal sensing platform in this work. At the hardware-level, this platform consists of a reconfigurable integrated circuit containing many commonly used signal-processing blocks and circuit components that can be connected in any configuration. At the software level, this platform provides a framework for abstracting this underlying hardware. We demonstrate how to quickly develop new applications on this platform, ranging from standard sensor interfacing techniques to more complicated intelligent pre-processing and wake-up detection. We also demonstrate how to integrate this platform with commonly used wireless sensor nodes and embedded-system platforms.

The limited power budgets of sensor networks necessitate some level of in-network pre-processing to reduce communication overhead. The low power consumption of analog signal processing (ASP) is well-suited for this task. However, the quick adoption of this technology has been restrained by the fact that ASP implementation requires a priori knowledge of the application space. Our solution to this challenge is to enable run-time reconfiguration through the use of a field-programmable analog array (FPAA). In the same way that reconfigurable digital systems allow system designers to change the infrastructure of digital blocks, an FPAA allows an application developer to change the infrastructure of, and even tune, ASP blocks without circuit-level expertise. We will demonstrate that an FPAA can be used to (1) facilitate the use of ASP to reduce power consumption, and to (2) allow run-time reconfigurability to maximize ASP impact.