Recent years have seen a surge in musical performances accompanied by generative agents. Artificial voices, timbres synthesized by neural networks, and agents that mirror or respond to human performers are rapidly taking the stage. In parallel, practitioners in human-computer interaction (HCI) and music technology have called for practice-based research that identifies the most salient affordances of these developments by examining their use in the real-world contexts of music making. To advance practice-based research on human-AI music creation, we present a longitudinal account of two months of codesign with top local jazz musicians, spanning early explorations, the identification of emerging goals, and rehearsals. Our work culminates in a public concert for a live audience of 97, featuring three pieces co-improvised with AI agents. Drawing on systems including VampNet, Somax2, and the jam_bot, each piece was tailored to the stylistic strengths of the performers and the unique strengths and limitations of each system. Through this extensive iterative process, we uncovered a wide range of design interventions, from augmenting GenAI systems with a guitar pedal to situate it in a loop-based creative practice, to enabling musicians to anticipate AI response by visually forecasting its predictions. Where musicians tended to rein in the wilder qualities of the generative systems, some audience members expected a human-AI performance to allow as much agency and spontaneity as possible. In post-concert reflection, musicians also expressed the desire to practice more which in turn could enable them to let the agency of the systems shine. They also encouraged future musicians to lean more into the uncertainty. Together, we see a unique practice emerging through this musician-AI live improv medium.

Recent advances in neural network architectures, such as the Transformer, have enabled a shift from task-specific models to unified foundation models, significantly enhancing generalization and scalability. In contrast, analog circuit design has traditionally relied on bespoke optimization models tailored to individual circuits. To address this gap, we propose M3, a novel unified reinforcement learning (RL) that concurrently optimizes multiple circuits with different topologies to meet target specifications, without requiring task-specific adjustments. The M3 framework employs the Mamba architecture, a recently emerging model regarded as a potential alternative to the Transformer. It combines model-based RL with a dynamic scheduling mechanism that adapts RL parameters to balance exploration (seeking novel designs) and exploitation (refining existing ones). Experimental results demonstrate that M3 successfully trains RL agents capable of simultaneously optimizing multiple circuits, having different topologies, to achieve target performance levels while prior RL-based methods are unable to do. This approach highlights the potential of developing a unified model for optimizing circuits across varying topologies and target specifications1.

As Moore’s law slows down, foundries and design houses are resorting to design technology co-optimization (DTCO) to squeeze more performance out of a technology node. However, the efficiency of EDA tools plays a key role in driving DTCO. The existing commercial parasitic extraction tools are not able to respond to a process parameter change efficiently. For example, it takes 25 minutes to re-generate a parasitic netlist for a mere layer thickness change using existing commercial tools. This runtime becomes the bottleneck for standard cell DTCO. In this work, we demonstrate a machine-learning-based method targeted on standard cells that can efficiently extract parasitic capacitance within seconds while maintaining competitive error distribution compared to the state-of-the-art rule-based 2.5D extraction method, which suffers from pattern mismatch since no real layout is provided at the pre-characterization stage. We extract patterns from actual standard cell layouts as training data for the ML model, and the model can predict coupling capacitance with unseen layer thickness within milliseconds.

Utilizing multibit flip-flops (MBFFs) in circuit implementation offers a considerable saving on the dynamic power dissipated at the clock networks. However, indiscreetly allocating MBFFs by grouping single-bit flip-flops at the logic synthesis or placement stage in order to greedily save dynamic power severely hinders a full applicability of useful clock skew scheduling to the individual flip-flops in MBFFs, failing in effectively optimizing circuit timing. This is because the two internal clock inverters, consequently, the clock skew value, in an MBFF are shared by all of the flip-flops in the MBFF. This work overcomes this inherent limitation of inflexibility in MBFFs for useful clock skew scheduling by proposing a comprehensive design and technology co-optimization (DTCO) framework. To this end, we devise a new layout of MBFF cells called multiskewed MBFF layout, in which different clock skew values can be set to the individual internal flip-flops at the cost of additional internal clock inverters. With the multiskewed MBFFs, we propose a three-step DTCO flow: 1) DTCO-based flip-flop clustering at the logic stage, which clusters flip-flops considering multiskewed MBFFs; 2) DTCO based on in-place MBFF debanking technique at the preroute stage to facilitate the full applicability of useful skew scheduling at the subsequent stages; and 3) DTCO utilizing MBFF cell layout diversification at the post-route stage, by which useful clock skew scheduling can effectively resolve timing violations. Through experiments with OpenCores benchmark circuits, it is shown that our proposed DTCO flow of reinforcing the effectiveness of useful clock skew scheduling on circuits with MBFF instances is able to reduce the worst and total negative slacks by 36.73% and 50.76%, respectively, while decreasing the clock and total power consumption by 43.46% and 22.70% over that produced by the conventional flow using a state-of-the-art commercial tool.

Large language models (LLMs) trained on massive corpora demonstrate impressive capabilities in a wide range of tasks. While there are ongoing efforts to adapt these models to languages beyond English, the attention given to their evaluation methodologies remains limited. Current multilingual benchmarks often rely on back translations or re-implementations of English tests, limiting their capacity to capture unique cultural and linguistic nuances. To bridge this gap for the Korean language, we introduce the HAE-RAE Bench, a dataset curated to challenge models lacking Korean cultural and contextual depth. The dataset encompasses six downstream tasks across four domains: vocabulary, history, general knowledge, and reading comprehension. Unlike traditional evaluation suites focused on token and sequence classification or mathematical and logical reasoning, the HAE-RAE Bench emphasizes a model’s aptitude for recalling Korean-specific knowledge and cultural contexts. Comparative analysis with prior Korean benchmarks indicates that the HAE-RAE Bench presents a greater challenge to non-Korean models by disturbing abilities and knowledge learned from English being transferred.

As the VLSI technology continues to scale beyond 5nm, a strong demand on the continuing layout reduction of standard cells is required. However, the standard cells with conventional FinFET or nanosheet-FET structure are becoming much hard to meet this requirement due to the lateral P-FET and N-FET separation. It has been widely accepted that Complementary-FET (CFET) is a promising technology, which stacks P-FET on N-FET or vice versa, to achieve this objective. In comparison with synthesizing the conventional FET based standard cells, two prominent optimization tasks in CFET based multi-row cell synthesis that significantly affect the cell quality, in terms of area and routability, are (1) determining transistor folding shapes and (2) determining placement order of transistors with fully secured vertical i.e., z-directional routing space on the stacked FETs as well as buried power rail (BPR). In this work, we propose an optimal solution to the combined problem of tasks 1 and 2. Precisely, we develop a search tree-based area-optimal method of transistor folding and placement, in which we accelerate the cost computation of partial solutions by formulating it into dynamic programming while performing a strict feasibility checking of securing in-cell vertical routing space of partial solutions by formulating and solving it into an instance of network flow problem. In the meantime, through experiment with benchmark circuits, it is shown that the CFET cells produced by our cell synthesizer are 5% smaller in size on average even with 38% shorter total metal length and 70% less use of metal2 for in-cell routing over the cells produced by the recent state-of-the-art CFET cell generator.

Resolving the design rule checking (DRC) violations at the pre-route stage is critically important to reduce the time-consuming design closure process at the post-route stage. Recently, noticeable methodologies have been proposed to predict DRC hotspots using Machine Learning based prediction models. However, little attention has been paid to how the predicted DRC violations can be effectively resolved. In this paper, we propose a pre-route DRC violation resolution methodology that is tightly coupled with fully compatible prediction model. Precisely, we devise different resolution strategies for two types of DRC violations: (1) pin accessibility (PA)-related and (2) routing congestion (RC)-related. To this end, we develop a fully predictable ML-based model for both PA and RC-related DRC violations, and propose completely different resolution techniques to be applied depending on the DRC violation type informed by the compatible prediction model such that for (1) PA-related DRC violation, we extract the DRC violation mitigating regions, then improve placement by formulating the whitespace redistribution problem on the regions into an instance of Bayesian Optimization problem to produce an optimal cell perturbation, while for (2) RC-related DRC violation, we manipulate the routing resources within the regions that have high potential for the occurrence of RC-related DRC violation. Through experiments, it is shown that our methodology is able to resolve the number of DRC violations by 26.54%, 25.28%, and 20.34% further on average over that by a conventional flow with no resolution, a commercial ECO router, and a state-of-the-art academic predictor/resolver, respectively, while maintaining comparable design quality.

In this paper, we propose a comprehensive physical design flow specifically tailored for Monolithic 3D (M3D) integration, a transformative technology for high-density and highperformance IC design in the post-Moore era. Unlike conventional RTL-to-GDS flows that heavily focus on utilizing commercial 2D design tools, our design flow delves deep into the suboptimal issues inherent in implementing cross-tier connections, which are not adequately addressed by 2D tools. Our proposed flow provides seamless optimization for such connections through three key design stages following pseudo-3D placement: (1) 3D routing-aware tier partitioning that induces subtle imbalances in cell area distribution between tiers to maximize the utilization of monolithic inter-tier vias (MIVs); (2) MIV-guided detailed placement that optimizes the placement by strategically utilizing reserved whitespace for enhanced 3D connections; and (3) MIV-aware 3D routing that takes full advantage of the finetuned placement result. Experiment results using open-source benchmark circuits in advanced 7nm technology nodes show that our proposed M3D design flow achieves up to 9.92% wirelength reduction per 3D net, resulting in 76.70% improvement in worst negative slack, and an equivalently improved 60.28% energy-delay-product over the state-of-the-art M3D design flow on average even with challenging design conditions. We provide valuable insights into various factors for efficient and high-quality M3D IC design with effective solutions.

Advanced technology nodes face challenges related to DRVs (design rule violations), primarily due to (1) pin inaccessibility and routing on congested region. While various ML (machine learning) techniques have been introduced to address these issues during placement, aggregating data on pin accessibility and routing congestion for ML model training has proven very challenging. This study presents an innovative ML-based approach to DRC (design rule check) hotspot prediction that effectively captures the combined impact of pin accessibility and routing congestion. Specifically, we introduce the concept of pin proximity graph, which accurately represents spatial information regarding cell I/O pins and pin-to-pin disturbance relationships. We then propose a novel ML model called PGNN, which seamlessly integrates GNN (Graph Neural Network) and U-net. In this approach, GNN handles the incorporation of pin accessibility information derived from the pin proximity graph while U-net extracts routing congestion information from grid-based features. Additionally, we solidify the capability of our prediction model toward ensuring the practical applicability and sustainability of our model by integrating two learning methodologies into our model training framework. Those are (1) transfer learning whose objective is to retain the same level of prediction accuracy in spite of not having enough data on the new process node and (2) incremental learning whose objective is to reduce the train time while maintaining the model accuracy in similar quality when new circuits are added.

Utilizing multi-bit flip-flops (MBFFs) in circuit implementation offers a considerable saving on the dynamic power dissipated at the clock networks. However, indiscreetly allocating MBFFs by grouping single-bit flip-flops at the logic synthesis or placement stage in order to maximally save dynamic power severely hinders a full applicability of useful clock skew scheduling to the individual flip-flops in MBFFs, failing in effectively optimizing circuit timing. This is because the two internal clock inverters, consequently, the clock skew value, in an MBFF are shared by all of the flip-flops in the MBFF. This work overcomes this inherent limitation of inflexibility in MBFFs for useful clock skew scheduling by proposing a comprehensive DTCO (design and technology co-optimization) framework integrating two viable techniques, called in-place MBFF debanking and skew driven cell layout diversification. Precisely, we proposed a two-step DTCO flow: (1) DTCO based on in-place MBFF debanking technique at the pre-route stage to facilitate the full applicability of useful skew scheduling at the subsequent stages and (2) DTCO utilizing MBFF cell layout diversification technique at the post-route stage, by which useful clock skew scheduling can effectively resolve timing violations. Through experiments with OpenCores benchmark circuits, it is shown that our proposed DTCO flow of reinforcing the effectiveness of useful clock skew scheduling on circuits with MBFF instances is able to reduce the worst and total negative slacks by 16.87% and 46.26% at the cost of 1.00% power overhead over that produced by the state-of-the-art conventional flow.

The significantly increased density of pins of stan-dard cells and the reduced number of routing tracks at sub-10nm nodes have made the pin access problem in detailed routing very difficult. To alleviate this pin accessibility problem in detailed routing, recent works have proposed to make a small perturbation of cell shifting, cell flipping, and adjacent cells swapping in the detailed placement stage. Here, an essential element for the success of pin accessibility aware detailed placement is the installed cost function, which should be sufficiently accurate in predicting the degree of routing difficulty in accessing pins. In this work, we propose a new model of cost function that is comprehensively devised to overcome the limitations of the prior ones. Precisely, unlike the conventional cost functions, our proposed cost function model is based on the empirical routing data in order to fully reflect the potential outcomes of detailed routing. Through experiments with benchmark circuits, it is shown that using our proposed cost function in detailed placement is able to reduce the routing errors by 44 % on average while using the existing cost functions reduce the routing errors on average by at most 15 %.

An accurate DRC (design rule check) hotspot prediction at the placement stage is essential in order to reduce a substantial amount of design time required for the iterations of placement and routing. It is known that for implementing chips with advanced technology nodes, (1) pin accessibility and (2) routing congestion are two major causes of DRVs (design rule violations). Though many ML (machine learning) techniques have been proposed to address this prediction problem, it was not easy to assemble the aggregate data on items 1 and 2 in a unified fashion for training ML models, resulting in a considerable accuracy loss in DRC hotspot prediction. This work overcomes this limitation by proposing a novel ML based DRC hotspot prediction technique, which is able to accurately capture the combined impact of items 1 and 2 on DRC hotspots. Precisely, we devise a graph, called pin proximity graph, that effectively models the spatial information on cell I/O pins and the information on pin-to-pin disturbance relation. Then, we propose a new ML model, called PGNN, which tightly combines GNN (graph neural network) and U-net in a way that GNN is used to embed pin accessibility information abstracted from our pin proximity graph while U-net is used to extract routing congestion information from grid-based features. Through experiments with a set of benchmark designs using Nangate 15nm library, our PGNN outperforms the existing ML models on all benchmark designs, achieving on average 7.8~12.5% improvements on F1-score while taking 5.5× fast inference time in comparison with that of the state-of-the-art techniques.

Monolithic 3D (M3D) is a revolutionary technology for high-density and high-performance chip design in the post-Moore era. However, it suffers from considerable thermal confinement due to the transistor stacking and insulating materials between the layers. As a way of reducing power, thereby mitigating the thermal problem, we propose a comprehensive physical design methodology that incorporates two new important items, one is blockage aware MIV (monolithic inter-tier via) placement and the other is 3D net ordering for routing, intending to optimize wire length. Precisely, we propose a three-step approach: (1) retrieving the MIV region candidates for each 3D net, (2) fine-tuning placement to secure MIV spots in the presence of blockages, and (3) performing M3D routing with net ordering to consider the fine-tuned placement result. We implement the proposed M3D design flow by utilizing commercial 2D IC EDA tools while providing seamless optimization for cross-tier connections. In the meantime, our experiments confirm that proposed M3D design flow saves wire length per cross-tier net by up to 41.42%, which corresponds to 7.68% less total net switching power, equivalently 36.79% lower energy-delay-product over the conventional state-of-the-art M3D design flow.

As the layout of standard cells is becoming dense, accessing pins is much harder in detailed routing. The conventional solutions to resolving the pin access issue are to attempt cell flipping, cell shifting, cell swapping, and/or cell dilating in the placement optimization stage, expecting to acquire high pin accessibility. However, those solutions do not guarantee close-to-100% pin accessibility to ensure safe manual fixing afterward in the routing stage. Furthermore, there is no easy and effective methodology to fix the inaccessibility in the detailed routing stage as yet. This work addresses the problem of fixing the inaccessibility in the detailed routing stage. Precisely, (1) we produce, for each type of cell, multiple layouts with diverse pin locations and access points by modifying the core engines i.e., gate poly ordering and middle-of-line dummy insertion in the flow of design-technology co-optimization based automatic cell layout generation. Then, (2) we propose a systematic method to make use of those layouts to fix the routing failures caused by pin inaccessibility in the ECO (Engineering Change Order) routing stage. Experimental results demonstrate that our proposed cell layout diversification and replacement approach can fix metal-2 shorts by 93.22% in the ECO routing stage.