Traditional statistical static timing analysis (SSTA) using available single-input switching (SIS) based gate delay libraries either ignore timing impact from multiple-input switching (MIS) or use single-corner (deterministic) models for MIS consideration. This paper presents a method for modeling the impact of MIS on statistical timing accurately using concepts of convolution and chain ruling. Experimental results in a commercial SSTA framework demonstrate negligible run-time overheads of modeling MIS while accurately exposing timing slack optimism in an SIS based flow of up to 17 pico-seconds on designs mapped to a 14 nanometer technology library. Prediction of timing critical paths due to MIS show excellent correlation to silicon hardware. Comparisons with prior work illustrate the accuracy improvements of the presented work.

Path tracing is a key requirement in providing various functionalities in a Static Timing Analysis (STA) tool. With growing design sizes and advancements in STA techniques like statistical timing analysis, path tracing techniques need to be more efficient and accurate. Naïve extensions of path tracing techniques for statistical timing analysis are found to be inefficient and inaccurate. In this paper, we present a novel Statistical Path Tracing (SPT) approach and illustrate its application in Common Path Pessimism Removal (CPPR). We demonstrate that SPT is more efficient and accurate when compared to a Deterministic Path Tracing (DPT) approach.

IBM's high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a transistor width tuner that optimizes performance and area. We also describe the application of electrical rule checking used to enforce consistent design practices. Finally, we discuss a macro extraction tool that determines parasitic resistance and capacitance of interconnect from a layout.