Ensuring accurate traffic perception and road safety in complex urban environments remains a significant challenge. Advanced traffic monitoring increasingly relies on deep learning, which requires large data volumes. However, existing datasets are often limited to CCTV video footage or focus on dynamic scenarios captured by sensors mounted on ego vehicles. This narrow perspective reduces the effectiveness of comprehensive traffic monitoring, particularly for LiDAR sensors, which typically capture only the vehicle’s viewpoint and miss critical areas such as intersections and pedestrian crossings. To address these limitations, we propose a holistic strategy for rapid data collection in urban settings using simulated 3D intersections. Our approach introduces a point cloud collection framework using static LiDAR sensors to provide a global view of the entire traffic scene. By incorporating randomized traffic patterns observed from multiple angles, this method generates a diverse, comprehensive dataset for object detection and instance segmentation, showcasing its advantages for benchmarking smart mobility applications.

Standard NNs should not be employed mindlessly in critical applications due to their incapability to express the uncertainty of their predictions. On the other hand, Bayesian Neural Networks (BNNs) can measure the uncertainty of their predictions. There are two methods for BNN inference, the Monte Carlo-based method, which requires the sampling of weights distributions and multiple inference iterations, and moment propagation, where the mean and variance of a normal distribution are propagated through the BNN. Hardware implementations of moment propagation BNN inference consume less power than Monte Carlo because they complete the inference in a single forward pass. However, because the propagation of distribution moments through nonlinear activation functions leads to large hardware designs, these functions are usually approximated by polynomials. Hardware implementations of moment propagation have been studied solely for fully-connected neural networks while lacking optimal accuracy due to the approximation of the ReLU activation function with a single polynomial term. Therefore, in this work, we add one more polynomial term in the approximation of ReLU, providing better accuracy with negligible additional hardware. We also propose a polynomial approximation for another common activation function, tanh, and extend the hardware implementation to Convolutional Neural Networks (CNNs). Experimental results demonstrated that the proposed approximation of ReLU outperforms the previously suggested single-term polynomial by achieving up to 5.9% higher accuracy with merely up to 0.029$W$power overhead.

The wide usage of the Clustered Regularly Inter-spaced Short Palindromic Repeats associated with the Cas9 enzyme (CRISPR/Cas9) system, which is one of the latest genome-editing methods, has shed light on pathways that were inconceivable before, from enhancing fruit nutrition to treating incurable diseases. The precise prediction of single guide RNA (sgRNA) on-target knockout efficacy poses a substantial challenge to the practical application of CRISPR/Cas9 systems. Although many Machine Learning (ML)-based techniques have yielded encouraging results, prediction accuracy still needs improvement. CRISPR/Cas9 datasets do not contain many examples for training the models. Generative Adversarial Networks (GAN)s are good at learning a model for generating new training data given a dataset. This work proposes a novel Machine Learning model that combines Convolutional Neural Networks and conditional GANs (coGAN)s to predict sgRNA on-target knockout efficacy. Experimental results showed that the proposed model could outperform other models proposed in the literature in regression and classification tasks for predicting the on-target sgRNA cleavage efficacy in CRISPR/Cas9 systems.

This study proposes a new algorithm for parameter estimation of the electric circuit model of Lithium (Li)-ion battery. The first-order battery-electric circuit model is considered in this work that resembles battery charging and discharging behaviors. The battery circuit element values have been modeled as polynomial equations with unknown coefficients. An accurate estimation of the battery circuit element values is profound to accurately find the battery State of Charge (SoC), an immeasurable quantity required in battery management systems (BMS). The ElectroStatic discharge algorithm (ESDA) is used in this study to estimate the unknown polynomial coefficients and, in turn, the values of the battery circuit elements. The accuracy of the proposed ESDA in estimating the battery circuit element values is compared to the recently proposed Artificial Hummingbird Optimization Technique (AHOT), Chameleon Swarm Algorithm (CSA), and Tuna Swarm Optimization (TSO). The results demonstrate the superiority of the proposed algorithm for charging and discharging in battery parameters estimation over the other algorithms with an accuracy gain of at least 10%.

Photovoltaic (PV) arrays, when subjected to Partial Shading (PS), exhibit several power losses due to diminished current across the array. Therefore, bypass diodes are connected across array modules to avoid the PS effect. Although they reduce the PS effect, the bypass diodes make the Power versus Voltage (P- V) relation of a PV non-convex. This paper investigates the Maximum Power Point Tracking (MPPT) problem under PS conditions to track the PV array's Maximum Power Point (MPP). Because previously proposed algorithms for this problem either failed to track the MPP or were computationally expensive, we propose a modified version of the Bat metaheuristic algorithm with dynamically narrowing search space (DNSS) exploration to avoid exploring low-power regions. The results show around 35 % gain in terms of rapidity and efficiency of the proposed metaheuristic approach in mitigating power losses compared to other existing algorithms.

The accurate decoding of ElectroEncephaloGraphy (EEG) signals would bring us closer to understanding brain functionality, opening new pathways to fixing brain impairments and devising new Brain-Computer Interface (BCI)-related applications. The impressive success of deep convolutional neural networks extracting information from raw data in computer vision and natural language processing has motivated their investigation into EEG signal decoding. Consequently, a number of deep convolutional neural network models with state-of-the-art performance have been proposed in the literature for EEG signal decoding. However, because all these works aimed to find the model architecture with the best decoding accuracy, the model's size was left unbounded in that exploration. Considering the model size in the design of deep convolutional neural networks for EEG decoding could make their implementation on low-power microcontrollers (that may be integrated into a wearable system) with limited memory feasible. Thus, in this paper, we search for the most accurate deep convolutional neural network on the BCI Competition IV 2a dataset that can also fit in a microcontroller with less than 256KB SRAM. Specifically, we use a Neural Architecture Search (NAS) algorithm that considers, apart from the model's accuracy, the model size, the latency, and the peak memory utilization when running the model's inference. We compare our models with the model with the best decoding accuracy in the literature on the BCI Competition IV 2a dataset (baseline). We show that the discovered models could achieve similar accuracy to the baseline model while shrinking the memory footprint during inference by a factor of ≈ ×20, with a speedup in latency of up to ×1.7 on average.

A better understanding of ElectroEncephaloGraphy (EEG) and ElectroCorticoGram (ECoG) signals would get us closer to comprehending brain functionality, creating new avenues for treating brain abnormalities and developing novel Brain-Computer Interface (BCI)-related applications. Deep Convolutional Neural Networks (deep CNNs) have lately been employed with remarkable success to decode EEG/ECoG signals. However, the optimal architectural/training parameter values in these deep CNN architectures have received little attention. In addition, new data-driven optimization methodologies that leverage significant advancements in Machine Learning, such as the Transformer model, have recently been proposed. Because an exhaustive search on all possible architectural/training parameter values of the state-of-the-art deep CNN model (our baseline model) decoding the motor imagery EEG and finger tension ECoG signals comprising the BCI IV 2a and 4 datasets, respectively, would require prohibitively much time, this paper proposes a model-based optimization technique based on the Transformer model for the discovery of the optimal architectural/training parameter values for that model. Our findings indicate that we could pick better values for the architectural/training parameters of the baseline model, enhancing the accuracy of the baseline model by 3.4% in the BCI IV 2a dataset and by 29.8% in the BCI IV 4 dataset.

With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ramps, while gate-interconnect interdependencies are stronger. Moreover, efficiency is a serious concern since repeatedly invoking a signoff tool during incremental optimization of modern VLSI circuits has become a major bottleneck. In this paper, we introduce a novel machine learning approach for timing estimation of gate-level stages using current source models and the concept of multiple slew and effective capacitance values. First, we exploit a fast iterative algorithm for initial stage timing estimation and feature extraction, and then we employ four artificial neural networks to correlate the initial delay and slew estimates for both the driver and interconnect with golden SPICE results. Contrary to prior works, our method uses fewer and more accurate features to represent the stage, leading to more efficient models. Experimental evaluation on driver-interconnect stages implemented in 7 nm FinFET technology indicates that our method leads to 0.99% (0.90 ps) and 2.54% (2.59 ps) mean error against SPICE for stage delay and slew, respectively. Furthermore, it has a small memory footprint (1.27 MB) and performs 35× faster than a commercial signoff tool. Thus, it may be integrated into timing-driven optimization steps to provide signoff accuracy and expedite timing closure.

Electricity generation using photovoltaic (PV) technology has become highly popular recently. However, natural barriers such as trees, buildings, bird drops, etc., cause partial shading (PS) on the PV surface resulting in high power losses. Bypass diodes used to mitigate the PS effect cause multiple peaks in the PV power delivery. The tracking of the optimal power peak can be considered an optimization problem with a continuously changing objective function due to different insolation conditions. All optimization strategies applied in previous works spanning from mathematical programming techniques to Machine Learning and the recently proposed Nature-inspired algorithms led to either sub-optimal maximum power or required extensive computations. This work presents an algorithm that combines the advantages of the previous works and avoids their loopholes. Experimental results indicate the superiority of the proposed algorithm over the state-of-the-art algorithm for the Maximum Power Peak Tracking problem.

The integration of more components into modern integrated circuits (ICs) has led to very large RLC parasitic networks consisting of millions of nodes that have to be simulated in many times or frequencies to verify the proper operation of the chip. Model order reduction (MOR) techniques have been employed routinely to substitute the large-scale parasitic model with a model of lower order with a similar response at the input-output ports. However, established MOR techniques generally result in dense system matrices that render their simulation impractical. To this end, in this article, we propose a methodology for the sparsification of the dense circuit matrices resulting from MOR of general RLC circuits, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. In addition, we describe a procedure for synthesizing the sparsified reduced-order model into an RLC circuit with only positive elements. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy.

As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models (CSMs) for accurate gate modeling. Industrial gate models, however, are precharacterized assuming capacitive loads, which poses significant challenges to the approximation of the highly resistive load interconnect with an effective capacitance ( Ceff). In fact, most related works are either computationally expensive or unable to approximate the output slew. Furthermore, they require additional precharacterization and ignore the Miller effect. In this article, we present an iterative methodology for fast and accurate gate delay estimation. The proposed approach accurately computes the driver output waveform, using closed-form formulas to calculate a Ceffper waveform segment, while accounting for their interdependence. Thus, it allows for variable analysis resolution exploiting an accuracy/runtime tradeoff. In contrast to prior works, our approach is compatible with conventional CSMs and considers the impact of Miller capacitance. We evaluate our method on representative driver-load test circuits consisting of interconnects with arbitrary RC characteristics and ASU ASAP 7-nm standard cells. The proposed method achieves 1.3% and 2.5% delay and slew root-mean-square percentage error (RMSPE) against SPICE, respectively. In addition, it provides high efficiency, as it converges in 2.3 iterations on average.

The integration of more components into ICs due to the ever increasing technology scaling has led to very large parasitic networks consisting of million of nodes, which have to be simulated in many times or frequencies to verify the proper operation of the chip. Model Order Reduction techniques have been employed routinely to substitute the large scale parasitic model by a model of lower order with similar response at the input/output ports. However, all established MOR techniques result in dense system matrices that render their simulation impractical. To this end, in this paper we propose a methodology for the sparsification of the dense circuit matrices resulting from Model Order Reduction, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy.

The integration of more components into modern Systems-on-Chip (SoCs) has led to very large RLC parasitic networks consisting of million of nodes, which have to be simulated in many times or frequencies to verify the proper operation of the chip. Model Order Reduction techniques have been employed routinely to substitute the large scale parasitic model by a model of lower order with similar response at the input/output ports. However, all established MOR techniques result in dense system matrices that render their simulation impractical. To this end, in this paper we propose a methodology for the sparsification of the dense circuit matrices resulting from Model Order Reduction of general RLC circuits, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy.

The verification of integrated Circuits (ICs) in deep submicron technologies requires that all mutual inductive effects are taken into account to properly validate the performance and reliable operation of the chip. However, the inclusion of all mutual inductive couplings results in a fully dense inductance matrix that renders the circuit simulation computationally prohibitive. In this paper, we present efficient techniques for the solution of the linear systems arising in transient analysis of large mutually inductive circuits. These techniques involve the compression of the dense inductance matrix block by low-rank products in hierarchical matrix format, as well as the development of a Schur-complement preconditioner for the iterative solution of the transient linear system (which comprises sparse blocks alongside the dense inductance block). Experimental results indicate that substantial compression rates of the inductance matrix can be achieved without compromising accuracy, along with considerable reduction in iteration counts and execution time of iterative solution methods.

Manufacturing process variation in sub-20nm processes has introduced ever increasing overhead in Static Timing Analysis (STA) in order to guarantee the reliable operation of the circuit. Chip designers apply corner-based analysis and add guard-bands to design parameters in order to take into account the impact of process variation on timing. However, the aforementioned techniques are either too slow as the number of design parameters proliferates with the integration of more components into a chip or inaccurate due to the assumption that the worst case delay resides at the corners of design parameters. In this paper, we present a novel statistical methodology, which relies on Extreme Value Theory (EVT), to estimate the worst case delay of VLSI circuits under variations in gate/interconnect parameters. Despite the previous statistical approaches toward maximum delay estimation, our methodology can be applied regardless of the underlying gate/interconnect delay model or any assumption about the distribution of the Arrival Time (AT) at every circuit node, making it very appealing for integration to any level of timing analysis abstraction (from spice-to-gate level) and provide fast yet accurate results. Experimental results on ISCAS85/ISCAS89 circuits show that the estimated maximum AT at the Primary Outputs (POs) can be within 5% of the true maximum AT, at the cost of a few thousand Monte Carlo simulations.

As integrated circuit process technology progresses into the deep sub-micron region, the phenomenon of process variation has a growing impact on the design and analysis of digital circuits and more specifically in the accuracy and integrity of timing analysis methods. The assumptions made by the analytical models, impose excessive and unwanted pessimism in timing analysis. Thus, the necessity of removing the inherited pessimism is of utmost importance in favour of accuracy. In this paper an approach to the common path pessimism removal timing analysis problem, TKtimer, is presented. By utilizing certain key techniques such as branch-and-bound, caching, tasklevel parallelism and enhanced algorithmic techniques, the approach described by this paper is able to handle any type and size of clock network trees and showed 100% accuracy combined with reasonable execution time within a straightforward solution context.

This paper introduces a novel approach towards the statistical analysis of modern high-speed I/O and similar communication links, which is capable of reliably to determine extremely low (∼10−12or lower) bit error rates (BER) by using techniques from extreme value theory (EVT). The new method requires only a small amount of voltage values at the received eye center, which can be generated by running circuit/system level simulations or measuring fabricated I/O circuits, to predict link BERs. Unlike conventional techniques, no simplifying assumptions on link noise and interference sources are required making this approach extremely portable to any communication system operating with very low BER. Our experimental results show that the BER estimates from the proposed methodology are on the same order of magnitude as traditional time domain, transient eye diagram simulations for links with BER of 10−6and 10−5operating at 9.6 and 10.1 Gbps respectively.