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Kishore Singhal

dblp:13/117 · DBLP profile ↗
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6ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5Human-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 63% Integrated circuit design · 37%

Topics — the 10 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.021992
Switched-capacitor simulation models for full-chips verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Polynomial splines for MOSFET model approximation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988
Electronic design automation › hardware verification and test
functional verification
0.011992
Switched-capacitor simulation models for full-chips verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation
hardware verification and test
0.011992
Switched-capacitor simulation models for full-chips verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › hardware verification and test › analog/mixed-signal verification
mixed-signal verification
0.011992
Switched-capacitor simulation models for full-chips verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
switched-capacitor circuits
0.011992
Switched-capacitor simulation models for full-chips verification · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › design for manufacturability › statistical design
design centering
0.011990
Technology CAD for competitive products · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation
technology computer-aided design
0.011990
Technology CAD for competitive products · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990
Electronic design automation
circuit simulation
0.011988
Polynomial splines for MOSFET model approximation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988
Integrated circuit design › analog and mixed-signal circuits
analog circuit design
0.011987
WATOPT -- An Optimizer for Circuit Applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Electronic design automation › logic synthesis
circuit optimization
0.011987
WATOPT -- An Optimizer for Circuit Applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987

Methods — techniques the papers use, named apart from their topics

graph-based clock configuration analysis · 0.0functional model generation · 0.0optimization · 0.0polynomial splines · 0.0mathematical programming · 0.0quadratic programming · 0.0
YearPublicationVenuePosition
2006 Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies
abstract
Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include inter-and intra-die variations of geometries, as well as process and electrical parameters. In this paper, pattern (i.e. density, width and space) dependent interconnect thickness and width variations are studied based on a well-designed test chip in a 90 nm technology. The parasitic resistance and capacitance variations due to the process variations are investigated, and process-variation-aware extraction techniques are proposed. In the test chip, electrical and physical measurements show strong metal thickness and width variations mainly due to chemical mechanical polishing (CMP) in nanometer technologies. The loop inductance dependence of return patterns is also validated in the test chip. The proposed new characterization methods extract interconnect RC variations as a function of metal density, width and space. Simulation results show excellent agreement between on-wafer measurements and extractions of various RC structures, including a set of metal loaded/unloaded ring oscillators in a complex wiring environment.
Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal
ACM Great Lakes Symposium on VLSI6
1992 Switched-capacitor simulation models for full-chips verification
abstract
Models and techniques used in a switched-capacitor functional model generator are described. The simulation models described are asynchronous with respect to the clock inputs, and the proposed models are useful for achieving functional verification of chips consisting of clock generating circuitry, switched-capacitor circuits, and other analog or digital blocks. Graph-based methods are used for each clock configuration to minimize CPU requirements. Continuous feedthrough of the analog signals is adequately handled. The program MODGENSC has been developed to generate the models directly from the circuit description in SWITCAP. With this capability, full-chip mixed digital/analog simulation is achievable and the simulation time is reduced significantly.>
Tom Chanak, Rakesh Chadha, Kishore Singhal
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
1990 Technology CAD for competitive products
abstract
Recent trends in the integration of process-, device-, and circuit-modeling tools and the current rapid emergence of Unix-based computing environments of networked workstations and computer engines makes possible user-friendly, task-based CAD systems for technology optimization, characterization, and cell design. The authors discuss these trends and identify opportunities to use technology CAD tools in the development of competitive technologies and products. It is shown that the ability to provide design centering and extreme-case analysis related to process variables has been a key to aggressive design of robust IC products. This capability results from efforts in the early to mid-1980's to establish integrated modeling systems such as MECCA, the application of general-purpose optimization capabilities such as WATOPT and CENTER, and recent advances in open and powerful computing environments (principally Unix-based distributed resources).>
Peter Lloyd, Heinz K. Dirks, E. James Prendergast, Kishore Singhal
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
1988 Polynomial splines for MOSFET model approximation
abstract
The approximation of MOSFET nonlinearities by use of polynomial splines was investigated for reducing both circuit model development time and model simulation cost. After a brief tutorial on spline functions, it is shown how the number of independent variables for the MOSFET simulation models in digital circuits is reduced by their use. A tableau formulation for generating splines is presented along with a storage-reduction technique for polynomial spline coefficients. Mathematical programming problems for one-, two-, and three-dimensional splines are given that result in accurate monotonic splines using few segments. Two spline segments are shown to provide sufficient accuracy in the one-dimensional case, while 4*4 and 2*5*5 segments provide sufficient accuracy in the two- and three-dimensional cases, respectively.>
James A. Barby, Jirí Vlach, Kishore Singhal
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
1987 WATOPT -- An Optimizer for Circuit Applications
abstract
A nonlinear constrained optimizer, WATOPT, targeted towards circuit applications is described. It utilizes a specially tailored quadratic program which reduces storage requirements and improves speed of computations. Three advanced designs in the frequency domain show application.
Rakesh Chadha, Kishore Singhal, Jirí Vlach, Ernst Christen, Milan Vlach
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1986 A Systems Approach to Three-Dimensional Multibody Systems Using Graph-Theoretic Models
abstract
The discipline of linear graph theory, which has been applied extensively to the analysis of electrical networks, is now extended to encompass general three-dimensional isolated rigid-body systems. The graph-theoretic models of a rigid body and its relevant components are discussed elaborately to pave the way for further studies in multibody systems. Utilizing the analysis based on system topology, the mathematical model of a mechanical system is derived by means of a hybrid formulation in which Euler parameters (or normalized quaternions) are incorporated to define the orientations of rigid bodies. A single body system serves as an illustrative example.
Jack C. K. Chou, H. K. Kesavan, Kishore Singhal
IEEE Trans. Syst. Man Cybern.3