Finding optimal solutions for Combinatorial Optimization (CO) problems is challenging. Compared to power-hungry cryogenic quantum computer and time-consuming classical computer, quantum-inspired Ising machine solves CO problems at room temperature with fast optimization speed, low power consumption, and low cost. Nevertheless, the Ising machine still faces several challenges: digital CMOS Ising machines increase interaction freedom at the cost of greater area and larger processing time; in analog Ising machine, oscillator spins find it hard to differentiate spin states without the assistance of the post-processing algorithm, and latch spins suffer from mismatches. To address these issues, we propose an oscillator-based 3-D CMOS Analog Ising Machine (CAIM) which adopts the 12-way toroidal Hexagonal Close Packed (HCP) structure, Supply-And-Bulk Injection Locking (SABIL), and dual-mode tunable coupler. The toroidal HCP structure exhibits >2 & times; interactions compared to conventional 3-D Ising machine, while SABIL and dual-mode tunable coupler settle oscillators to a bistable ground state 2.2 & times; quicker with an 8.5 & times; wider lock range (within 5 cycles). The proposed CAIM successfully solves 3-D max-cut problems and achieves a normalized Hamiltonian energy of more than 0.98 with a maximum perfect accuracy prevalence (PAP) of 91.67%. Measurement results on a sample random Max-Cut instance demonstrate that CAIM converges to within 1.7% of the reference optimum in 5 cycles.

This article presents an energy-efficient 13-bit high-speed SAR-assisted cyclic ADC. The$1^{\text {st}}$stage 6-bit SAR ADC coarsely quantizes the input signal. The proposed charge-reused 2-bit/cycle cyclic ADC doubles the conversion speed with 50% reduction in capacitor number. Owing to the comparator noise suppression circuit and mismatch robustness of the cyclic ADC, an interstage gain of only$2\times $is required, which significantly relaxes the amplifier design and improves its total harmonic distortion (THD). Fabricated in 40nm 1P8M CMOS, the proposed SAR-assisted cyclic ADC achieves 13b resolution with SNDR and SFDR of 66.5dB and 80.1dB, respectively, with a Nyquist-rate input at 70MS/s without calibration while consuming 0.88mW power, yielding FoMSand FoMWof 175dB and 6.9fJ/conv., respectively. The ADC demonstrates a sub-1dB SNDR variation across the measured 9 chips, presenting the robustness against variations.

Capacitively-Coupled Instrumentation Amplifiers (CCIAs) are widely used as AC-coupled, low-noise amplifiers in many multi-channel, area-intensive sensor interface applications. However, the need for a trade-off between the front-end gain and CCIA area, imposed by the input capacitance, restricts the miniaturization of such sensors. We propose a Complementary Transimpedance Boosting (CTB) technique to relieve this challenging gain versus area trade-off. The proposed CTB applies to both the DC and AC paths of a CCIA. CTB also reduces AC gain degradation, suppressing low-side gain peaking of the frequency response without significantly increasing input-referred noise. The Gain-Noise-Area Efficiency (GNA) and Gain-Power-Area Efficiency (GPA) factors are also introduced for holistic comparisons with other front-end amplifiers regarding noise, gain, and power consumption. CTB-based CCIAs (CTB-CCIA) are fabricated in 0.18$\mu$m CMOS, with the highestsingle-stageAC gain of 289 V/V achieved. Occupying only 0.011 mm$^{2}$, a conventional CCIA with the same area will have 14.4$\times$less gain while requiring at least two stages. The CTB-CCIA has a competitive NEF of 4.92 within a signal bandwidth of 0.21 Hz – 8.7 kHz, suitable for multi-channel applications.