Biomedical sensors operate under low supply voltage, in low frequency domains, and require low power consumption. This paper proposes a new power-efficient, low-pass and band-pass fully differential biquad suitable for bio-signal acquisition, based on Folded Gain Boosting Source-Follower (FGB-SF). This solution does not require a Common-Mode Feedback (CMFB) and it offers a wide tuning range. Implemented using 0.18 μm TSMC technology, it achieves the lowest power consumption reported in the literature (0.46 nW), a high Dynamic Range (DR) of 43.8 dB, and an IIP3 of 6.55 dBm with 250 Hz bandwidth. Post-layout simulations demonstrate stability under Montecarlo and PVT variations. The occupied area is only 69.5 μm x 51.3 μm and exibits the lowest FOM compared with the state of the art.

Bioimpedance spectroscopy allows determining the characteristics of a medium through its electrical response. In dynamic events, the approach based on sequential bioimpedance analyses at different frequencies is not appropriate due to its duration. Simultaneous multi-sine spectroscopy is a suitable alternative to obtain the bioimpedance spectrum in a fast way. The practical implementation of this technique requires the design of programmable filters, which include tunable transconductors, for the separation of the different frequency components of the response signal. Two circuit techniques to design a transconductor with tunable transconductance ( G m ), are proposed. The originality of the solution relies on the subtraction of the G m of two voltage-to-current sections, thus leading not only to a wide tuning range of the effective G m but also to a low value of this circuit parameter. The transconductors were designed and fabricated in 180 nm CMOS technology to operate with 1.8 V. Measurements on 9 samples of the silicon prototypes show that mismatch prevents achieving the very low G m obtained in simulations, even though the deviations are within the variation ranges determined by a Montecarlo analysis. The SF and DP solutions display mean values for the maximum/minimum G m of 10.29 μ A/V/149.5 nA/V and 10.1 μ A/V/302.8 nA/V, respectively, which represent transconductance tuning ratios of 68.8 × and 33.4 × , also respectively. Other remarkable feature of this proposal is that the second-order transconductor-capacitor ( G m - C ) bandpass filters (BPFs), designed for signals separation, incorporate multiple-output versions of the proposed transconductors, thus leading to a reduction of area occupation and power consumption. The BPFs were designed to have nominal values of the gain at the centre frequency and of the quality factor of 0 dB and 2.83, respectively, whereas the centre frequency can be programmed over approximately one decade.

This paper introduces an innovative approach to designing a mismatched current mirror with a fully unbalanced output, significantly reducing the minimum supply voltage requirements for Regulated Cascode Current Mirror (RCCM) Physical Unclonable Functions (PUFs). Leveraging body-driven feedback mechanisms, the proposed circuit reliably operates with supply voltages as low as 0.3V, maintaining stable power consumption through a reference bias current. The resulting PUF achieves remarkable energy efficiency, consuming only 0.3 fJ per bit, without compromising statistical performance. It exhibits a response bias of 49.42%, a reliability of 99.483%, and a uniqueness of 50.176%. Validation of this novel approach is conducted through simulations and measurements on a 130nm CMOS test-chip, considering a nominal supply voltage of 0.3V, ±10% supply voltage variations, and a temperature range from 0°C to 75°C. Rigorous experimental verification on 20 chip samples, along with detailed explanations of design methodologies, underscores the robustness and practicality of the proposed Body-PUF design. Comparative analyses against state-of-the-art literature reveal that the Body-PUF outperforms previous PUF designs in Figures of Merit (FOM), making it promising for real-world authentication scenarios. Its outstanding trade-off between performance and practicality positions it as a compelling solution for secure applications, including Internet of Things (IoT) devices and other security-critical systems.

Nonlinear calibration allows enhancing the performance of analog and radiofrequency circuits by digitally correcting nonlinearities. Often, calibration is performed in the complex baseband domain, and Volterra models are used. These models have hundreds of coefficients, and easily become computationally unfeasible. This is worse in complex Volterra models, because high-order Volterra terms require summing multiple products of the input signal. We propose a generalized complex Volterra model based on one relaxation of Volterra theory: all the nonlinear monomial terms in the model are considered separately, even if they correspond to a single real coefficient in complex Volterra theory. This produces more accurate models, though with a larger number of coefficients. We thus extensively prune the model by means of OMP and OBS techniques. The resulting models have fewer coefficients and/or better accuracy than conventional Volterra models, resulting in a significantly improved accuracy-complexity trade-off. These results are validated in the experimental calibration of a commercial IF amplifier. The resulting model achieves the same accuracy, with 9 free parameters and 34 multiplications, as the standard Volterra model with 12 parameters and 266 multiplications, resulting in a 25% reduction in the number of parameters, and an 87% reduction in the number of multipliers.

High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasing filters in the multi-GHz range. Asynchronous Time-Interleaved (ATI) digitizers also need low-pass filters before digitization, and additional requirements on their design are set by this specific application. In integrated solutions, inductor-less filters are important for minimizing the chip area footprint. In this paper, we present the design of a 6th-order inductor-less 10GHz low-pass filter implemented in the STMicroelectronics SiGe BiCMOS55 process. It can be used as anti-aliasing filter for conventional 30GS/s digitizers or at the output of a 40GS/s ATI digitizer. We exploit positive feedback to synthesize the active inductor based on a stacked topology, minimizing the number of current branches, and thus power consumption. Analysis and design guidelines for the biquad are presented. The filter exhibits a bandwidth of 10GHz with a power consumption of 43mW, a THD of −45dB and an SNR of 43dB with an input amplitude of 710mV peak-to-peak differential. Extensive corner and Monte Carlo post-layout simulations have been carried out to highlight the robustness of the circuit to PVT and mismatch variations. Experimental results have confirmed very good agreement between measured and simulated performance, validating the proposed design flow.

In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Current Mode Logic (FMCML) and an analytical design strategy to optimize its performance are presented. To validate the proposed models and design procedures we have used a 28nm, Fully Depleted Silicon on Insulator (FDSOI), CMOS technology to design and simulate a divide-by-8 circuit. The designed frequency divider exhibits a maximum operating frequency of about 15GHz with a power consumption of only 110μW thus confirming the advantages of the proposed approach.

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology.

The Time Enclosed Logic (TEL) is a dual-rail signaling protocol used in the context of cryptographic circuits in order to maintain the time enclosing of information leakage also in the presence of capacitive mismatch. The capacitive mismatch, due to non-perfectly balanced differential routing, provides additional data-dependent leakage that a malicious adversary could use to recover secret information from a hardware implementation. In this work, a novel TEL-compatible standard-cell based flip-flop for cryptographic application is presented. The new flip-flop is intended to be compatible also for FPGA applications. The novel standard-cell architecture has been tested with energy-defined metrics adopting a 4-bit register as case study, implemented in 40nm CMOS process. It has been found that it is able to reduce the data-dependence of the power consumption up to ×0.05 also in the presence of strong mismatch if compared to unprotected CMOS. A comparison with WDDL and MDPL has shown that NED and NSD are remarkably reduced (up to ×30 and ×40 respectively), and their values are independent from the capacitive mismatch in the novel flip-flop architecture.

In this paper, a novel modeling framework is proposed to quickly estimate the delay variability of logic paths due to random variations, and evaluate the related design margin. The analysis shows that the popular fan-out-of-4 metric F04 can capture the impact of technology and voltage on the delay variations of logic paths. Once those contributions are isolated, the impact of random variations on standard cells' delay is accounted for by means of cell-specific coefficients that are evaluated in a preliminary library characterization phase. The proposed framework is very general and applicable from sub-threshold to nominal voltage, and provides the designer with a deep insight into the main delay variability contributions in a path. It also predicts the impact of design modifications (e.g., logic restructuring, cell up-sizing), and is well suited for pencil-and-paper calculations. Case studies involving three critical paths extracted from designs ranging from microprocessors to specialized hardware show adequate accuracy, with a delay variability error being typically less than 10%.

This paper presents the design of a novel low-voltage high-speed D-latch circuit suitable for nanometer CMOS technologies. The proposed topology is compared against the low-voltage triple-tail D-latch and its advantages are demonstrated both by simulations, under different performance/power consumption tradeoffs with a 40-nm CMOS technology, and theoretically, thanks to a simple model of the propagation delay derived for both low-voltage topologies. In order to further demonstrate the advantages of the proposed topology, it has also been used to design a D flip-flop (DFF), where thanks to the feature to need just 1 clock differential pair; a further speed improvement is achieved over the conventional triple-tail topology. Indeed, by comparing a two-stage frequency divider designed using both the triple-tail DFF and the proposed folded DFF, a 54% improvement in the maximum operating frequency is found when using the proposed folded DFF.

Emerging low-power radio triggering techniques for wireless motes are a promising approach to prolong the lifetime of Wireless Sensor Networks (WSNs). By allowing nodes to activate their main transceiver only when data need to be transmitted or received, wake-up-enabled solutions virtually eliminate the need for idle listening, thus drastically reducing the energy toll of communication. In this paper we describe the design of a novel wake-up receiver architecture based on an innovative pass-band filter bank with high selectivity capability. The proposed concept, demonstrated by a prototype implementation, combines both frequency-domain and time-domain addressing space to allow selective addressing of nodes. To take advantage of the functionalities of the proposed receiver, as well as of energy-harvesting capabilities modern sensor nodes are equipped with, we present a novel wake-up-enabled harvesting-aware communication stack that supports both interest dissemination and converge casting primitives. This stack builds on the ability of the proposed WuR to support dynamic address assignment, which is exploited to optimize system performance. Comparison against traditional WSN protocols shows that the proposed concept allows to optimize performance tradeoffs with respect to existing low-power communication stacks.

We demonstrated the feasibility of the adaptive frequency compensation approach to design maximum- and constant-bandwidth feedback amplifiers. A basic CMOS amplifier exhibiting 66-dB dc gain and 310-MHz gain-bandwidth product was designed. For closed-loop gains ranging from 1 to 10, the closed loop bandwidth was found never lower than 401 MHz. A similar amplifier with equal gain-bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed-loop bandwidth decreased to 33 MHz when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, while the other main opamp performance parameters remain almost unchanged compared to the standard solution.

The main drawback of current-mode interface circuits for on-chip capacitive sensors is that the measurement sensitivity is adversely affected by the sensor parasitic capacitance. This causes a strong limitation in the range of applicability of CM interfaces. In this paper we propose a technique that avoids this problem and allows the design of high-performance CMOS interfaces. The proposed solution is based on a feedback loop that, during an autotuning phase, sets the driving current level, hence ensuring virtually the same accuracy irrespectively of the parasitic capacitance. The technique was implemented and designed using a 65-nm CMOS technology. Simulation results are found in close agreement with those theoretically expected, resulting also in an increased accuracy of the capacitive variation detection.

This paper investigates the design of a data flip-flop compatible with the three-phase dual-rail pre-charge logic (TDPL) family. TDPL is a differential power analysis (DPA) resistant dual-rail logic style whose power consumption is insensitive to unbalanced load conditions, based on a three phase operation where, in order to obtain a constant energy consumption, an additional discharge phase is performed after pre-charge and evaluation. In this work, the TDPL basic gates operation is shortly summarized and the TDPL flip-flop implementation is reported. A part of an encryption algorithm is used as case a study to prove the effectiveness of the proposed circuit. Simulation results in a 65 nm CMOS process show an improvement in the energy consumption balancing in excess of 10 times with respect to the state of the art.

In this paper, the effectiveness of the recently proposed Leakage Power Analysis (LPA) attacks to cryptographic circuits is analyzed in the presence of process variations. Reference circuits (e.g., S-BOX, crypto core) were designed in various logic styles, and their robustness against LPA attacks was comparatively evaluated through Monte Carlo simulations in 65 nm. Analysis allowed for better understanding the impact that process variations have on the outcome of LPA attacks, which is an aspect that is not understood currently. Results show that LPA attacks are rather effective also under die-to-die and within-die process variations. Moreover, the comparison between different logic styles showed that standard CMOS logic circuits are extremely vulnerable to LPA attacks. Other logic styles that are robust against traditional Differential Power Analysis (DPA) attacks were also compared. Interestingly, analysis showed that these logic styles are still vulnerable to LPA attacks. Hence, LPA attacks are an even greater threat to Smart Cards information security, compared to DPA attacks. Moreover, traditional methods to protect Smart Cards against DPA attacks are ineffective in counteracting LPA attacks, thereby showing that a significant research effort will be needed to counteract LPA attacks with suitable solutions that ensure high security standards.

This paper investigates the design of a dual-rail precharge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. The proposed logic is based on a novel encoding concept where the information is represented in the time domain rather than in the spatial domain as in a standard dual-rail logic. In this work, a logic family which exploits the proposed concept has been implemented. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and routing capacitances. An improvement in the energy consumption balancing up to 50 times and an area reduction up to 60% with respect to the state of the art have been obtained.

A cascode current mirror with auxiliary body-driven feedback loop is proposed. Main performance parameters are analytically evaluated and compared to those of a conventional high-swing cascode and of a recently-proposed body-driven topology. Simulations are also provided confirming improvements in the achievable output resistance (important for short channel technologies), DC accuracy, and input dynamic range. Linearity, bandwidth, noise and voltage requirements are substantially the same of the conventional high-swing cascode solution.

In this paper we consider a side-channel attack on a chaos-based random number generator (RNG) based on power consumption analysis. The aim of this attack is to verify if it is possible to retrieve information regarding the internal state of the chaotic system used to generate the random bits. In fact, one of the most common arguments against this kind of RNGs is that, due to the deterministic nature of the chaotic circuit on which they rely, the system cannot be truly unpredictable. Here we analyze the power consumption profile of a chaos-based RNG prototype we designed in 0.35 mum CMOS technology, showing that for the proposed circuit the internal state (and therefore the future evolution) of the system cannot be determined with a side-channel attack based on a power analysis. This property makes the proposed RNG perfectly suitable for high-security cryptographic applications.

A CMOS differential amplifier cell for minimum supply requirements is presented. The solution uses transistors in strong inversion and an original biasing scheme that exploits the bulk terminals of the transistor pair to accurately set the quiescent current and provide common-mode control. As a result, we avoid the use of the tail current source adopted in traditional differential stages. An implementation based on an auxiliary switched-capacitor network used in the feedback control loop is proposed and theoretically examined. Measurements on a prototype fabricated in a standard 0.35- mum technology (with threshold voltages around 0.5 V) and powered with 1.2 V show an error in the bias current of about 15% with respect to the expected value. It was found that the obtained overall performance is comparable to that of a traditional long-tailed differential pair that uses a higher supply of 1.5 V.

In this paper we present a gain enhancement technique for very low-voltage deep sub-micron amplifiers based on the use of a CCH-based negative impedance converter. Relaxed specifications on the current conveyor allow an easy implementation of this technique in a sub-1 V environment, where common topologies such as the cascode and the differential pair cannot be used. An example implementation in a 65-nm CMOS technology, using plusmn0.35 V supply voltage and a simple 6-transistor CCH topology, shows a 15.5-dB gain enhancement with a good robustness against process variations.

In CMOS smart sensors and microsystems it can be very convenient to integrate both analog and digital circuits in the same chip; since the supply voltage for high-accuracy, high- precision interfaces should be as immune from disturbances as possible, low drop out regulators are often necessary. Here we show a CMOS, dual op amp, fast, low drop out regulator which allows to diminish the power supply gain by orders of magnitude up to very high frequencies.

Temperature measurement is becoming increasingly important in integrated circuits and microsystems; nevertheless, existing techniques for the integration of high accuracy, high precision temperature sensors are not optimal for deep sub-micron CMOS processes. Here we describe a low voltage, low power, compact, high accuracy, high precision temperature sensor for deep sub-micron CMOS systems; our approach takes advantage of charge balancing and charge sharing for low current consumption, does not use resistors for compactness, and takes advantage of both PTAT and autozero techniques for high accuracy and high precision; the circuit can be operated at low supply voltages. As a proof of concept, we report transistor level simulations in a standard 0.13 mum process; the sensor only sinks about 6 muA from a 1.2 V supply voltage, achieving a power dissipation as low as 7.2 muW.

We present a flexible mixed-signal architecture for the synthesis of an n-port analog network. It exploits a field programmable gate array as digital processing element and second generation current conveyors as analog input/output blocks. To validate the approach, a prototype is realized for the basic case of a two-port network and experimental results in agreement with those expected are provided.

The design flow of a digital cryptographic device must take into account the evaluation of its security against attacks based on side channels observation. The adoption of high level countermeasures, as well as the verification of the feasibility of new attacks, presently require the execution of time-consuming physical measurements on the prototype product or the simulation at a low abstraction level. Starting from these assumptions, we developed an exploration approach centered on high level simulation, in order to evaluate the actual implementation of a cryptographic algorithm, being it software or hardware based. The simulation is performed within a unified tool based on SystemC, that can model a software implementation running on a microprocessor-based architecture or a dedicated hardware implementation as well as mixed software-hardware implementations with cycle-accurate resolution. Here we describe the tool and provide a large set of design explorations and characterizations based on actual implementations of the AES cryptographic algorithm, demonstrating how the execution of a large set of experiments allowed by the fast simulation engine can lead to important improvements in the knowledge and the identification of the weaknesses in cryptographic algorithm implementations.

A novel power analysis technique for CMOS cryptographic hardware based on leakage power consumption measurements is presented. Algorithms and models to predict the input vector for maximum and minimum leakage currentallin CMOS gates are reviewed. Extensive transistor level simulations on a simple CMOS crypto core are presented. Leakage current measurements carried out on an ASIC for cryptographic applications implemented in a 0.13 um CMOS technology are reported. The results of this work show that leakage current can be exploited as a side channel by an attacker to extract information about the secret key in cryptographic hardware implemented in short channel CMOS technologies.

Pipeline analog-to-digital converters (ADC) are widely used to achieve high resolution and moderately high sampling frequency. In typical implementations, linearity is often limited by capacitor mismatch and finite amplifier gain. The impact of these non ideal effects on the overall linearity of the ADC has been addressed in this paper, obtaining a model to estimate total harmonic distortion (THD), given capacitors' sizing and amplifiers' gain. This model enables the designer to analyze the impact of error sources in each stage separately, and to perform Monte Carlo simulations. In this way, design rules can be obtained to properly size each multiplying digital-to-analog converter (MDAC) in the first stages of the design process.

We describe the first ever reported continuous time, gain enhanced voltage amplifiers which are almost insensitive to mismatch of active devices. Though the proposed approach is general, as a preliminary test we have designed a voltage amplifier in a standard 0.35μm CMOS process; Monte Carlo simulations demonstrate both a significant gain enhancement and its robustness against spread of process parameters.

The authors describe low voltage current and voltage references which only use MOSFETs in strong inversion and pnp substrate transistors; both the references exhibit very good performance in terms of power supply rejection and do not require compensation capacitances; the minimum supply voltage is about 0.8V for the current reference and 1.2V for the voltage reference.

We propose a linearization technique, for CMOS differential pairs employing resistive source degeneration, which exploits the bulks of the pair as additional control terminals. Simulations were performed using a 0.25-μm process, on an example design powered with 2.5V and 1 mA. Compared to the traditional source-degenerated transconductor, the proposed approach allows a THD reduction in the voltage-to-current conversion by 10dB, for an input differential signal of 0.5Vppand for frequencies up to 100MHz.

A CMOS high-linearity transconductor useful for IC filtering applications is presented. It is based on a feedback unity-gain amplifier driving a resistor to achieve linear voltage-to-current conversion. Simulation results are provided on a design example using a 0.35-mum technology, powered from a 3.3V supply, and using a total dc current of 150 muA. The 3-dB bandwidth was 630 MHz and HD3, onto a load resistor of 20kOmega, was -82 dB at 1MHz.

The susceptibility of cryptographic devices to attacks based on power analysis can be both significantly and efficiently tested at early design steps. The results from a real case application show the advantages of the approach.

Attacks based on a differential power analysis (DPA) are a main threat when designing cryptographic functions for implementation on chip cards. In this paper, a dynamic and differential lookup table (LUT) is presented and evaluated on a case study simulation. The proposed circuit shows a power consumption independent from the input data and can be employed to implement combinatorial functions in cryptographic processors when a high resistance against tampering is required. A typical application is the design of nonlinear functions (for example, substitution boxes) since protecting them with less expensive countermeasures (for example, random masking) implies a significant overhead. In the adopted case study, a 1.02 percent spread in the power consumption has been obtained when parasitic capacitances are taken into account. Moreover, a comparison with a static complementary metal-oxide semiconductor implementation shows an acceptable overhead in terms of area and power consumption.

The threat of side-channel attacks (SCA) is of crucial importance when designing systems with cryptographic hardware or software. The FP6-funded project SCARD enhances the typical micro-chip design flow in order to provide a means for designing side-channel resistant circuits and systems. Appropriate SCA-simulation tools and SCA analysis for the designer of secure systems are part of the project goals. We consider these enhancements for traditional design flows of micro-chips as necessary in order to enable the design for the next generation of secure and dependable devices. SCARD is in its final phase, the final result a SCARD chip designed by using the developed design flow is currently implemented

A distance-dependent non-linear statistical model of the active part of a very short-length HEMT-based MMIC, expressed in terms of principal components, is presented. A statistical model has been extracted for 0.1 mum GaAs HEMT devices and MMIC's. Validation of the model is presented, based on principal component analysis and statistical hypothesis testing

A novel current measuring technique is introduced which promises to substantially enhance power analysis attacks against cryptographic co-processors. The proposed technique exploits an active circuit to measure the instantaneous current consumption of a device under attack while supplying, at the same time, the device with a stable voltage. Higher gain-bandwidth product, higher sensitivity and lower insertion error are the main advantages with respect to a resistor-based measurement. Experimental results when the proposed circuit is used to measure the current consumption of an FPGA are reported and the achievable advantage in terms of sensitivity is discussed too

A new, patent pending, concept for a random bit generator, suitable to be integrated in a cryptographic device, is presented. The proposed circuit exploits the relative jitter between two identical ring oscillators sharing the same delay elements and shows several advantages with respect to other oscillator-based generators reported in the technical literature. In particular, the generator is stateless and therefore easily testable accordingly to what is reported in (Bucci, 2005). Moreover, the generation throughput is automatically adapted to the available noise in the circuit thus guaranteeing the statistical quality (minimum entropy) of the generated bits. To validate the proposed circuit, simulation results on a 0.12mum CMOS process are reported

A behavioral model of a sample-and-hold circuit is presented, focused on the distortion due to the nonlinear switch on-resistance. A simplified expression for third-order harmonic distortion has been derived, by using a quadratic MOS model where body effect is neglected, and it has been extended to the case of a transmission gate switch. Both the behavioral model and the distortion estimation have been validated by comparison with Cadence simulations, and very low errors have been obtained over a wide range of circuital and signal parameters

We propose an inverting closed-loop amplifier architecture providing high input impedance and a theoretically zero gain error, without requiring infinitely large loop gain. The architecture is based on two nested amplifiers closed in feedback through a resistive network. A straightforward CMOS implementation is also given. Simulations using a 0.35-mum CMOS process are found in agreement with expected results. Monte Carlo simulations have also shown the robustness of the proposed approach against process tolerances

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PLL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies

This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by an on-chip digital controller. The associated design flow allows us to quantitatively predict the impact of the method on the expected yield in a specific design. We present the architecture scheme, the theoretical foundation, the estimation circuits used, and two application case studies, referring to an industrial 0.13-/spl mu/m CMOS process data. The approach results to be remarkably effective at high operating temperature. In the presented case study, initial yields below 14% are improved to 86% by using a single controller and a single set of estimation circuits per die.

The design of a high-speed IC random number source macro-cell, suitable for integration in a smart card microcontroller, is presented. The oscillator sampling technique is exploited and a jittered oscillator which features an amplified thermal noise source has been designed in order to increase the output throughput and the statistical quality of the generated bit sequences. The oscillator feedback loop acts as an offset compensation for the noise amplifier, thus solving one of the major issues in this kind of circuit. A numerical model for the proposed system has been developed which allows us to carry out an analytical expression for the transition probability between successive bits in the output stream. A prototype chip has been fabricated in a standard digital 0.18 /spl mu/m n-well CMOS process which features a 10 Mbps throughput and fulfills the NIST FIPS and correlation-based tests for randomness. The macro-cell area, excluding pads, is 0.0016 mm/sup 2/ (184 /spl mu/m /spl times/ 86 /spl mu/m) and a 2.3 mW power consumption has been measured.

A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-f/sub T/ silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 2/sup 23/-1 PRBS data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps.

Clock disabling for power management has been implemented in some microcontrollers, but the wake-up time of Xtal/PLL-based systems is incompatible with fast interrupt response. On the other hand, hardwired on-chip clocking has been used for dedicated circuits. We illustrate the design issues of a general-purpose microcontroller core with a programmable on-chip fully-digital clock generator. The CPU is compatible with the PIC16C57 instruction set and supports software-controlled clocking modes-ranging from 44 MHz up to 124 MHz; on-line self-tuning of the maximum full-speed frequency in case of peak-performance requirements; ultra-fast wake-up even with totally disabled clock generator-namely 8.6 ns.