On the aged society coming soon, many studies have explored homecare technologies. In this work, the activities at home are captured by a panoramic camera located at the center of a living room, and then analyzed and classified into standing, walking, sitting, falling, and watching television. First, the background subtraction scheme accompanied with shadow removal, and morphological operators of erosion and dilation is used to find out moving subjects, and TV on/off switching. Second, the parameters associated with the subject height, the distance between the camera and subject, and the distance map between subject contour points and centroid are computed to derive features for recognizing activities of standing, walking, sitting, and falling where the Support Vector Machine (SVM) classifier is employed. Additionally, the moving object similar to a parallelogram shape is identified as a TV set. Third, the majority voting in a picture segment of 10 pictures is adopted to determine the final recognition result. When subject sitting and TV on occur simultaneously, this situation is treated as an activity of watching TV. The experimental results reveal that our activity recognition system can achieve the accuracy rate up to 91.1%. The error rates associated with subject height and distance estimations are around 5.5% and 8.2%, respectively. The accuracies of TV on and off detection are close to 95.9% and 100.0%, respectively. Therefore, the proposed activity recognition system exhibits a superior performance for homecare applications.

In full-c hip elecrothermal analysis, the substrate is usually discretized into a lumped 3-D network to simulate the heat flow, which is computationally inefficient due to the numerous internal nodes represen ting the substrate interior. Y et traditional interconnect model reduction techniques are not v ery effectiv e at handling complex mlti-port networks with large port counts. In this work we overcome this limitation b y applying time-domain approximation techniques such as ARWE and Prony's method to further simplify the reduced substrate thermal netw ork. Experiments show that our method provides highly accurate simulation results with performance improvement in the range of 2x to 5x.

The dramatic increase of power consumption in very large scale integration circuits has led to high operating temperature and large thermal gradient, thereby resulting in serious timing and reliability concerns. Temperature-tracking is thus becoming of paramount importance in modern electronic design automation (EDA) tools. In this paper we present two thermal placement tools for standard cell and macro cell design styles respectively. They are aimed at reducing hot spots in a design without compromising traditional design metrics such as area and wire length. We developed a compact substrate thermal model that can be used by the placer to calculate the temperature profile of a placement efficiently, or to convert the user-specified temperature constraint into the corresponding power distribution constraint as an alternative placement objective. As a result, our method is much more efficient than directly employing temperature profile simulation during the placement process. The simulation results show noticeable improvement of thermal distribution over the traditional placement algorithm, with little impact on area and wire length of the final layout.

Due to interactions through the common silicon substrate, the layout and placement of devices and substrate contacts can have significant impacts on a circuit's ESD (Electrostatic Discharge) and latchup behavior in CMOS technologies.Proper substrate modeling is thus required for circuit-level simulation to predict the circuit's ESD performance and latchup immunity.In this work we propose a new substrate resistance network model, and develop a novel substrate resistance extraction method that accurately calculates the distribution of injection current into the substrate during ESD or latchup events.With the proposed substrate model and resistance extraction, we can capture the three-dimensional layout par&tics in the circuit as well as the vertical substrate doping profile, and simulate these effects on circuit behavior at the circuit-level accurately.The usefulness of this work for layout optimization is demonstrated with an industrial circuit example.

In this work we present a standard cell placement tool that aims at reducing hot spots while optimizing traditional design metrics such as area and wire length.By using the superposition principle and the concept of tmnsfer thernaal resistance, we first convert the temperature differential constraint to its corresponding power distribution constraint.Dealing directly with power distribution avoids time-consuming temperature calculation during placement.The power distribution constraint is then gradually tightened during the placement process to produce improved temperature profile.Our simulation results show noticeable improvement of thermal distribution over the traditional placement algorithm.The worst case increase in total wire length is less than 3%, and we observe no noticeable area increase.

Accurate simulation of transient device thermal behavior is essential to predict CMOS VLSI circuit failures under electrical overstress (EOS). In this paper, we present an efficient transient electrothermal simulator that is built upon a SPICE-like engine. The transient device temperature is estimated by the convolution of the device power dissipation and its thermal impulse response which can be derived an analytical solution of the heat diffusion equation. New fast thermal simulation techniques are proposed including a regionwise-exponential (RWE) approximation of thermal impulse response and recursive convolution scheme. The recursive convolution provides a significant performance improvement over the numerical convolution by orders of magnitude, making it computationally feasible to simulate CMOS circuits with many devices. I. Introduction Smaller devices, higher packing density and rising power consumption lead to dramatic temperature increases in deep submicron VLSI circuits. C...