Criticality metrics is a type of predictive models used in VLSI design. This work demonstrates that timing in physical design could be substantially improved if circuits were subjected to timing criticality analysis prior to layout and new criticality metrics were used to drive layout system. These new metrics are computed as ratios of net physical characteristics to the net delay bounds determined by an optimal bounds computation algorithm. Attempts to develop criticality metrics prior to layout were made before, but these metrics were not based on the bound ideology. The paper provides probabilistic interpretation of new criticality metrics and derivation of some important properties of these metrics. Evaluation of net criticality by new metrics can be easily merged with any layout system that allows weights to be assigned to nets on placement and/or routing steps. The methodology has been tested with a commercial layout system from a leading CAD provider. When the new criticality information was supplied to a basic commercial standard cell placer and router, timing was improved by 29.5% for the set of testcases. The achieved result is 12% better than timing generated by a targeted timing-driven layout system from the same provider. All additional computations related to the new criticality metrics require only negligible increase in run time of the basic layout system.

An application of constructive successive augmentation methodology to VLSI placement under constraints on routability, area and timing is described. To improve effectiveness of decision making, the placement algorithm uses adaptive and look-ahead procedures. This methodology was implemented in the placer-router JUNE for macrocell-library-based sea-of-gates design style with over-the-cell routing. JUNE achieves high utilization of area and timing requirements for real-life designs.>

Predictions of path criticalities are included into a constructive timing-driven placement procedure.These predictions are periodically performed through the placement process and are interlaced with placement steps.New emerging critical paths are treated preferentially improving convergence of the procedure.Consequently, timing of final placement is improved.Real 20K CMOS sea-of-gates designs illustrated the methodology.

An analytical method for general floorplan design and optimization is proposed. This method is based on a mixed integer programming model and application of a standard mathematical software. The method allows arbitrary combinations of rigid and flexible modules. Various objective functions such as chip area, interconnection length, timing delays or any combination of them are permitted. Routing space is estimated by the global router. Experimental data are provided.>

An adaptive timing-driven layout system, called JUNE, has been developed. The constructive algorithm, which combines placement with the global routing, constructs a placement satisfying timing and routability constraints. The placement problem for each macro is solved hierarchically as a sequence of two optimization problems followed by an adaptive correction procedure. Experimental results for industrial sea-of-gates chips confirmed effectiveness of this approach.

An analytical method for general floorplan design and optimization is proposed. This method is based on a mixed integer programming model and application of a standard mathematical software. The method allows arbitrary combinations of rigid and flexible modules. Various objective functions such as chip area, interconnection length, timing delays or any combinations of them are permitted. Routing space is estimated by the global router. Experimental data are provided.