Zijian Chen, Xueguang Ma, Shengyao Zhuang, Ping Nie, Kai Zou, Sahel Sharifymoghaddam, Andrew Liu, Joshua Green, Kshama Patel, Ruoxi Meng, Mingyi Su, Yanxi Li, Haoran Hong, Xinyu Shi, Xuye Liu, Hosna Oyarhoseini, Nandan Thakur, Crystina Zhang, Luyu Gao, Wenhu Chen, Jimmy Lin. Proceedings of the 64th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers). 2026.

To empower diverse Internet of Things applications, collaboration among resource-constrained devices becomes essential for effective task completion with complex service requirements, time constraints, and resource conditions. Under such complexities, trust becomes a key mechanism for effective collaborator selection, by leveraging both direct experience and peer recommendations. However, selecting reliable collaborators for new tasks remains challenging due to the changing task requirements blocking reuse of previous trust evaluations (TEs). While indirect trust from recommendations saves evaluation time, unattended recommender-specific characteristics such as capability and reliability adversely affect its usefulness. These challenges motivate us to develop disruptive trust fusion mechanisms for accurate and efficient TEs under changing conditions. For this purpose, we propose an original concept of trust permeability for new task-specific TEs, effectively integrating historical TEs and recommendations for new task-specific TEs. By decoding task-specific trust into task success parameters (TSPs), we develop permeable pathways fully exploiting existing TEs and enable collaborator selections for new tasks. Specifically, we propose a task permeable trust-based collaborator selection (TPTCS) mechanism which decodes existing TEs of potential collaborators from old tasks, forming sets of TSPs, and adaptively combines them with all previous task-specific TEs and quality recommendations for new tasks with new requirements. Eliminating the impacts of changing task requirements, the proposed TPTCS creates permeable pathways for rapid task-specific TEs under new task requirements, accelerating collaborator selection. During the combination, TEs are weighted between the decoding process and quality recommendations. Numerical results demonstrate TPTCS outperforms comparison mechanisms in selecting reliable collaborators for new tasks.

This paper aims to address the challenge of wireless authentication without security server support by proposing a novel dynamic encryption scheme based on the shared experiential history at different layers between communicating peers for enhanced peer-to-peer authentication. By utilizing an initial physical layer observation and less noisy cross-layer attributes over time as shared historical secrets and source of dynamicity, an ever growing historical log is established, enabling dynamic encryption key generation for passive authentication. The proposed peer-to-peer authentication scheme is further enhanced by a channel-aware k-means quantization and mapping method which reduces the effect of observation noise from the physical layer attributes while increasing the efficiency and entropy by finding the optimal k-value. Both mathematical analysis and numerical simulation results are provided to evaluate the scheme’s performance.

In this paper, we describe backchan.nl, a web based backchannel system that focuses on providing greater audience participation during question and answer sessions. The system allows audience members to use a web-based service to propose questions and comments, and to vote on the questions of others. Top rated submissions are projected into the presentation space where audience members, moderators, and panelists can see them. We discuss the results of deploying this system at many different kinds of conferences and relate those results to the particular design of our system, demonstrating how backchannel systems can be more than just shared chat rooms. From our experience with this work, we discuss the broader implications of configurable mediated social spaces and how subtle design decisions can influence user experience

New processors, both embedded and general purpose, often have conflicting design requirements involving space, power, and performance. Architectural features and compiler optimizations often target one or more design goals at the expense of the others. This paper presents a novel architectural and compiler approach to simultaneously reduce power requirements, decrease code size, and improve performance by integrating an instruction register file (IRF) into the architecture. Frequently occurring instructions are placed in the IRF. Multiple entries in the IRF can be referenced by a single packed instruction in ROM or LI instruction cache. Unlike conventional code compression, our approach allows the frequent instructions to be referenced in arbitrary combinations. The experimental results show significant improvements in space and power, as well as some improvement in execution time when using only 32 entries. These advantages make packing instructions into registers an effective approach for improving overall efficiency.