This work introduces SENSOTERIC, a multi-partner project that aims at leveraging the properties of emerging Reconfigurable Field Effect Transistors (RFETs) to develop a sensor platform. RFETs will be used for a generic sensor interface and for a dedicated transducer element. In the first case, our goal is to develop an analog front-end interface that can be tuned at runtime to adapt to different environmental conditions and be used in a broad spectrum of applications. This feature shall be enabled by the polarity-control and negative differential resistance characteristics of the reconfigurable devices employed, that are co-integrable on industrial CMOS processes such as 22 nm FDSOI. In the second case, we want to exploit the intrinsic nature of these doping-free devices to yield better 1/f noise performances when compared to classic CMOS transducers. Moreover, the presence of un-gated areas on top of the channel of these devices makes them the perfect candidates to be functionalized. In this early-stage overview of the project, we will introduce the key features and the vision that make SENSOTERIC a unique contribution towards smart sensing solutions in environmental monitoring and healthcare.

Reconfigurable field-effect transistors (RFETs), allowing dynamic run-time switching between n- and p-type operation, are already considered a viable CMOS add-on technology to enable adaptive computing concepts. Beyond that, exploiting the multi-gate architecture of RFETs can also be beneficial for analog circuits but has been less explored. Here, we experimentally demonstrate an adaptive current mirror based on Ge RFETs with the ability of electrostatic compensation of device-to-device variations, enabling an ideal current mirror that can even be switched between n- and p-type operation. Furthermore, the IOUT/IIN-ratio can be adjusted electrostatically without the need for additional devices. This enhances the abilities of traditional current mirrors that are not adjustable after manufacturing without the need for complex additional circuitry.

This work in progress innovative practice paper intends to report on the outline and the ongoing progress of the EU-project GreenChips-EDU, which has been started in October 2023, and intends to fundamentally redesign educational microelectronics programs especially but not limited to students and professionals. One of the major goals is the design of a new microelectronics master program to which six European universities are contributing. The contents of this program will be substantially enhanced with green electronics contents innovative teaching methods. Other work will be done in the field of a new MBA program, self-standing modules for professionals, and a new microelectronics bachelor designed by one university of applied sciences.

This innovative practice work-in-progress paper de-scribes an integrated course to introduce students to challenges in real world Printed Circuit Board (PCB) design. With the increasing complexity and speed of modern electronics, PCBs have become an integral part of electronic systems. Thus, acquiring knowledge in the field of PCB design is of great importance for aspiring engineers. At the same time the cost to manufacturing PCBs has fallen considerably, that even advanced processes are within reach of design courses taught at the university level. In the lectures, the PCB design workflow is introduced to establish a baseline between all learners. Part selection, schematic capture and creating a layout of a two-layer PCB is demonstrated live. Design rules are established, allowing more effective design reviews. The students acquire knowledge on advanced topics, such as multilayer technology, signal integrity and manufacturability. Exercises allow students to consolidate the most important learnings with impulse discussions. An integrated lab is successfully implemented and encourages students to practice PCB design. Using open-source software throughout the course lowers the barrier for students to get started with their designs,

Oscillator-based Ising machines (OIMs) are specialized in solving combinatorial optimization problems, that can be represented as the Ising model. They exploit the interaction of (integrated) electrical oscillators in a configurable network for the computation. Such systems naturally evolve towards a ground state, which forms a solution to the problem quickly and energy efficiently. This work presents the design of our 400 oscillator node chip in a 28nm technology. The focus is on the analog oscillator and coupler circuits, which determine the computing performance. Weighted optimization problems with up to 6-bit resolution can be solved within just 714ns. A comprehensive experimental analysis based on a versatile benchmark set is provided. We discuss the computation process and investigate the impact of multiple factors including the randomness of the initial oscillator phases, the frequency mismatch, the coupling strength, and the locking strength. A small range of parameters like the coupling strength and locking strength exists, which show the highest accuracy. Extensive benchmarks achieve an accuracy compared to the best-known solution of more than 94.5% for problems with equal weights and 89.8% for weighted problems. This emphasizes, that carefully designed oscillator-based Ising machines (OIMs) are not only fast, but can find solutions near the global optimum.

We present a compact optical programmable ASIC-based tag for the identification of novel drug candidates, requiring no external components. Our tag aims for a time and cost-efficient solution to keep track of compounds during the split and pool synthesis. The ASIC is self-powered by integrated solar cells and optimized for intensive light in the range of 10Mlx. This intensive illumination can cause unwanted leakage currents in p-n junctions. Therefore, extensive care was taken to provide shielding for sensitive parts of the circuit and measurements prove the effectiveness. The ASIC is manufactured in a 0.6µm process including special devices like EEPROM and photodiodes. Our tag contains an oscillator, optical receiver, reference voltage, and a digital controller. A custom optical communication protocol provides an energy-efficient data link to the smart tag with continuous power transfer.

This practice work-in-progress paper describes an innovative laboratory course designed to introduce a heterogenous cohort of undergraduate students from various fields of engineering and science to the principles of designing and analyzing complex electronic systems. The course utilizes a self-developed drum machine as a visual and acoustic project with a gradually increasing level of complexity throughout the lab sessions. Through active participation students acquire an understanding of SPICE simulations, test & measurement equipment, and printed circuit board (PCB) assembly. The course is mandatory for students pursuing a bachelor's degree in electrical, mechatronic, biomedical, computational, and information system engineering, and is also attended as an optional module by computer science and physics students. In the winter term of 2022, the course returned to the lab after the COVID-19 pandemic and was attended by more than 200 students. The laboratory experiments are supported by complementary activities, such as SPICE simulations of the circuits as preparation, and lab reports written in LaTeX to introduce the students to scientific writing. Instructional videos and consultation hours are offered to assist with SPICE simulation and LaTeX. During the physical lab sessions, students work in groups of three in a traditional laboratory environment, with student tutors available to provide guidance offered in the form of minimal help. Overall, the presented lab course is an innovative and engaging method of teaching electronic systems. The self-developed drum machine provides a visually and audibly stimulating project, allowing students to learn practical skills and develop their theoretical knowledge.

Solving optimization problems is becoming increasingly important for many applications in today's world. Various software solvers and digital hardware accelerators are designed to speed up the computation while decreasing energy consumption. However, NP-complete problems like the maximum-cut are still inefficient to solve using traditional computing methods. The usage of specialized analog coupled oscillator networks is an upcoming fast and energy-efficient option. In order to compete with digital counterparts, a similar solution accuracy at significantly increased speed is required. However, reaching a very good solution with such analog-oriented principles is still a major challenge. The system proposed here focuses on a best possible accuracy and speed, while area and power consumption are of minor priority. Experimental benchmarking shows that the computed solutions reach 95% accuracy and more of commercial software, while the actual computation takes just 714 nanoseconds.

This Innovative Practice Work in Progress Paper presents a comprehensive approach to convert an undergrad hands-on electronics lab to an e-learning experience. Special care was taken to make the format interactive as well as to encourage teamwork between students. The conversion was made to conform with the social distancing measures implemented as a response to the COVID-19 pandemic. Instead of relying on pre-recorded lessons, the lab was offered through live video sessions. Multiple cameras were used to make it easy for students to follow the instructor performing the experiment. Students worked together in teams they had chosen at the beginning of the semester throughout the entire course, giving team members the opportunity to get to know each other or strengthen existing bonds. During the live sessions, the teams were repeatedly sent to breakout rooms to discuss and vote on questions related to the execution of the experiments and the measurement results. The votes, which were carried out using the Moodle learning management system (LMS), were then discussed in the plenary, and the course of the experiment was adjusted accordingly. Using data of student participation from the LMS and the results of a detailed survey, the success of the implemented measures can be proven empirically. 88.2 % of students found that the interactive elements helped them to stay concentrated during the live sessions. 79.6 % agreed that the breakout rooms improved cooperation within their team and 72.8 % plan to stay in touch with their team members.

This innovative practice work-in-progress paper presents the outline of a bachelor level medical engineering lab that comprises electronical sensor signal processing. It explains how to teach and educate medical technology students the entire signal processing chain up to medical interpretation based on the practically relevant, widespread example of pulse oximetry. The various analog circuit blocks and the required post-processing with a microcontroller are discussed, as well as the interaction of all blocks to form the pulse oximeter system. For this purpose, the students are divided into small teams of three and receive a printed circuit board developed specifically for the experiment. With this board it is possible to extract certain parts of the signal processing measurement chain and analyze them with different tools, e.g. wave generator and oscilloscope. The accompanying handout guides and challenges students through the complex analysis of pulse oximetry, with subtasks to assist them. Tutors are available to support students with questions or if they get stuck. The aim of this practical exercise is for the students themselves to understand which individual steps are required and how they interact in order to obtain a valid measured value at the end. They learn the practical relevance and application of various electronic components and filter circuits, as well as the subsequent digitization and post-processing with the help of a microcontroller. In addition, the participants will familiarize themselves with the use of various measuring devices. The associated handout and its tasks do not provide step-by-step instructions. The students are encouraged to think creatively in their groups and to engage in group discussions so they understand the problem and find a solution for each subtask. After solving each subtask, the group receives feedback from a tutor who explains whether the solution to the task is right or wrong and whether there could have been smarter ways. By the end of the exercise, the students will have understood the complete signal path in depths from the sensor to the interpretation of the measured value and all the difficulties involved, based on a modern medical technology application.

We explore relationships between dynamics of emotion (arousal and valence) and topical stability in political discourse in two diachronic corpora of Austrian German. In doing so, we assess interactions among emotional and topical dynamics related to political parties as well as interactions between two different domains of discourse: debates in the parliament and journalistic media. Methodologically, we employ unsupervised techniques, time-series clustering and Granger-causal modeling to detect potential interactions. We find that emotional and topical dynamics in the media are only rarely a reflex of dynamics in parliamentary discourse.

The domain of German polarity dictionaries is heterogeneous with many small dictionaries created for different purposes and using different methods. This paper aims to map out the landscape of freely available German polarity dictionaries by clustering them to uncover similarities and shared features. We find that, although most dictionaries seem to agree in their assessment of a word’s sentiment, subsets of them form groups of interrelated dictionaries. These dependencies are in most cases an immediate reflex of how these dictionaries were designed and compiled. As a consequence, we argue that sentiment evaluation should be based on multiple and diverse sentiment resources in order to avoid error propagation and amplification of potential biases.

Reconfigurable FETs (RFETs) are ambipolar transistors featuring the ability to conduct both electrons and holes, which is often achieved through the use of silicon nanowires or similar gate-all-around topologies. In this article, we present initial results for standard cell synthesis based on our planar RFET device, featuring top-down planar silicon based technology, lower fabrication complexity than nanowire approaches and a high operating temperature robustness. We first introduce the device physics by explaining the structure and the operating principle on device level. We also summarize recent device optimizations to increase drive current and achieve symmetry between N- and P-type conduction. Next to CMOS-style standard cells, we present a reduced transistor count XOR cell and analyze timing. Transient simulations are performed entirely in TCAD to accurately show device performance. Further we describe extraction of relevant parameters of these circuits for usage in synthesis tools and compare our standard cells to a similar 180nmSOI technology. Afterwards we perform timing analysis for a full adder and explore the boundaries of our device with a larger cryptographic accelerator core.

This work presents an all-digital multiphase DLL and phase shifter. A Phase-to-Digital Converter is used as a linear phase detector with 6 bit resolution and up to 76.9 MS/s sample rate at 2.5 GHz. A digitally controlled shunt-capacitor delay element makes use of the parasitic capacitance of transmission gates to provide a linear delay characteristic with 0.82 ps step size. This allows the use of a digital low-pass filter instead of an analog one and simplifies the control loop design resulting in an all-digital circuit that scales well with technology. A 7 bit phase interpolator with a PVT compensation loop is implemented to generate a phase shiftable clock signal with fine resolution. The digital DLL and phase shifter occupy 0.0048 mm2of active area in a 65 nm CMOS process and consume 3.9 mW from a 1.2 V supply. The measured RMS random jitter is 1.2 ps for the DLL and 1.4 ps for the phase shifter respectively.

A wearable, low cost and power efficient early breast cancer detection device is proposed. Bioimpedance spectroscopy (BIS) and near infrared spectroscopy (NIRS) are used. The NIRS and BIS sensors differentiate between normal and cancerous breasts according to their optical and electrical properties respectively. The bioimpedance spectroscopy sensor measurements are carried out by a multi-step frequency sweep. The near infrared spectroscopy sensor uses multi-wavelengths LEDs with optical filters. The results obtained by NIRS and BIS sensors are combined together in the control unit. A custom designed mobile application is connected with the device through Bluetooth. The proposed device was tested in vitro using tissue like mimicking phantoms stimulating the electrical and the optical properties of the normal and cancerous breast tissues. The proposed system shows accuracy of 99.3% and low power consumption of 80mW.

This work presents a Phase-to-Digital Converter (PDC) synthesisable from a standard cell library that enables the measurement of phase and duty-cycle of high-speed clocks. The resolution and sample rate of the PDC can be adjusted by the choice of the frequency of an additional input clock. This allows the use of the PDC in closed-loop systems for phase or duty-cycle adjustments and provides a way to minimize the power consumption of the circuit. Also a calculation method is proposed to model the PDC's behavior with respect to jitter. The design is tested on an FPGA with up to 650 MHz and implementation results at 2.5 GHz in a 65 nm CMOS process show the potential use of the PDC for phase alignment and duty-cycle adjustment in multi-gigabit transceivers with low hardware cost and low power.

A wideband large dynamic range RF logarithmic power detector is presented in this work. The power detector is realized as a successive detection logarithmic amplifier and is fabricated using SiGe BiCMOS technology. The detector has a dynamic range of 64 dB and a sensitivity of -56 dBm at the center frequency of 1.5 GHz when considering a ± 1 dB error range. For the same error range, the dynamic range is larger than 58 dB for operating frequencies up to 2.3 GHz. The dynamic range is larger than 50 dB over the entire frequency range from 100 MHz to 3 GHz for an error range of ± 1.5 dB. The detector draws 9.91 mA current from a 3.3 V supply for a power consumption of 32.72 mW and its core occupies 0.064 mm2 area. The detector is intended for use in an RF transceiver ASIC for Fiber-To-The-Home applications.

Test compression hardware blocks such as EDT are utilized in large industrial designs to compress scan test data in order to decrease scan test time and volume. During pattern generation for EDT-based designs, some faults cannot be detected due to linear dependency and insufficient encoding capacity of EDT. These faults called EDT Aborted (EAB) faults cause a notable coverage loss in some designs. In this work, a new approach is proposed to form scan chains such that the number of EAB faults decreases and the test coverage increases. The approach places scan flipflops corresponding to care bits at appropriate positions in order to reduce linear dependency during pattern generation. The approach is totally automated and has been integrated into the existing design flow. The experimental results on the industrial designs show that the new approach decreases the number of EAB faults significantly and achieves a high test coverage.

A Real-Time Sleep Detection and Warning System for Driver's Safety Based on EEG is proposed and implemented to ensure the safety for the drivers and pilots. This system is implemented to estimate and measure the driver attention, the percentage of oxygen in the blood of the driver and to check if driver is failing a sleep. The design and implementation of oxygen saturation sensor is also provided. In addition this system contains a Real time vital signs monitoring system to measure the vital signs values. The proposed system achieved an Accuracy of 96.3%, 100% of sensitivity, 92.4% of Predictability and 93% Specificity. The accuracy, predictability and specificity of the vital signs monitoring system is increased by 2%, 3% and 1%, respectively.

In order to be able to handle an arbitrary amount of static communication segment faults in NoC-based MPSoCs, a flexible fault tolerance mechanism has to be applied. In this contribution, we present a flexible and scalable approach for fault-tolerance in NoCs, which - in contrast to existing circumvention techniques - can in principle handle any number of static faults in the routing network. It doesn't require routing restrictions (as static routing/source routing) and can basically be combined with any static or adaptive minimal or non-minimal routing algorithm. The needed additional hardware effort is low and the increase of the time for computation of routing decisions is reasonably low as well. The presented dependability technique can work hand-in-hand with a task scheduler/mapped and is applicable in critical, mixed-critical and non-critical application scenarios.

This paper analyses the non-idealities of a second generation current conveyor (CCII) in advanced CMOS technologies. Primary sources of errors in the CCII are identified and their effects are analyzed with respect to its application as an integrator for delta sigma modulators. An improved CCII integrator architecture and a robust calibration algorithm are proposed to negate the CCII errors. The proposed integrator is used in the design of a 4thorder CCII based delta sigma modulator, simulation results of which reveal the advantages of proposed solution. The modulator designed in a 1V/90nm technology has a 78/70/46 dB DR and 77/69/45 dB SNDR for bandwidths of 2/4/10 MHz and clock frequency of 160 MHz respectively.

A high throughput architecture is proposed for an efficient implementation of the Advanced Encryption Standard (AES) Algorithm. The presented architecture is adapted for AES encryptor-only as well as integrated AES encryptor/decryptor designs. The SubBytes/InvSubBytes operations are implemented using composite field arithmetic in order to exploit the sub-pipelining advantage within the loop-unrolling methodology. The proposed architecture minimizes the critical path delay through the modification of the SubBytes/InvSubBytes as well as the KeyExpansion modules. Compared to previously reported AES encryptors and integrated AES encryptors/decryptors designs, the proposed architecture provides an efficiency improvement of 61% and 29% respectively.

This paper presents a integrated high voltage digital-to-analog converter array, which is designed by using a 0.35μm high voltage CMOS technology(AMS H35), and can be applied in high voltage applications up to 120V. The DAC array has 16 high voltage DACs controlled by a digital controller on chip. To fulfil the requirement of communication system with reconfigurable antenna implemented using materials which have voltage dependent capacitance, the DACs are designed to have 8 bits of resolution. In order to improve the accuracy and decrease the required area, each independent DAC is implemented by a low voltage DAC and a high voltage amplifier for boosting the controllable output voltage. Since the current consumption from the high voltage power supply is only 1.28mA, it is possible to be powered by a charge pump which generates high voltage power supply from a battery. The proposed HV DAC array can drive up to 16 individual channels of antenna array with different voltages from 0V to 120V. It will greatly reduce the complexity and cost of mobile applications required high voltage. The feasibility is proved by post-simulation result.

Charge pump circuits are currently becoming a realistic alternative to the switching regulators in high voltage generation applications, especially in fully integrated circuit systems. This paper discusses several stabilization methods to improve voltage performance and robustness of integrated high voltage charge pumps. All the discussion and measurements are based on a monolithic integrated high voltage charge pump chip adopting an innovative circuit architecture and advanced clock scheme to overcome drawbacks of conventional charge pump circuit architectures. The possibility to integrate the stabilizing parts into the entire circuit system is also analyzed.

The advantages of moving from 2-Dimensional Networks-on-Chip (NoCs) to 3-Dimensional NoCs for any application must be justified by the improvements in performance, power, latency and the overall system costs, especially the cost of Through-Silicon-Via (TSV). The trade-off between the number of TSVs and the 3D NoCs system performance becomes one of the most critical design issues. In this paper, we present a fast and optimized task allocation method for low vertical link density (TSV number) 3D NoCs based many core systems, in comparison to the classic methods as Genetic Algorithm (GA) and Simulated Annealing (SA), our method can save quite a number of design time. We take several state-of-the-art benchmarks and the generic scalable pseudo application (GSPA) with different network scales to simulate the achieved design (by our method), in comparison to GA and SA methods achieved designs, our technique can achieve better performance and lower cost. All the experiments have been done in GSNOC framework (written in SystemC-RTL), which can achieve the cycle accuracy and good flexibility.

Hybrid network on chip architecture is proposed for high system performance, so with the increase in the number of IP blocks it improves the three main parameters which are throughput, latency and power dissipation better than traditional wired network on chip. Hybrid Mesh-Ring architecture has shown the advantages of using both wired and wireless links in the same network which shows a great performance in Network on Chip (NoC). Two models of Mesh-Ring Architecture are proposed one is based on wired and wireless links which is hybrid model and the other model is based on wired links only which is wired model. The hybrid model has improved the performance in Latency by 20 % as compared to wired model. Throughput has increased by 31 % compared to throughput of wired model and Power-dissipation has decreased by 11 % compared to wired model.

In high-speed communication systems, adaptive equalizers are widely applied to improve signal integrity in both master chip and slave chip. In this paper, a novel architecture with the equalizers applied only in the master chip is proposed for the low-power design through adaptive equalizer training. The system architecture is verified by implementing the receiver equalizer training at the circuit level and the transmitter equalizer training using different algorithms: 1) direct calculation 2) LMS algorithm 3) pilot signal/peak detection in Matlab/Simulink. Results show that LMS algorithm improves the vertical and horizontal eye opening by more than 30% and 10%, respectively. Furthermore, the proposed architecture can achieve 411mW per channel, which is a two-fold reduction in the power dissipation with respect to the conventional architecture. To adapt the concept, Graphic DDR5 is taken as a study case.

Advanced high-speed source-synchronous systems such as GDDR5 use multiple source-synchronous clocks to increase memory bandwidth. Therefore, well-defined phase relationships among multiple clocks are required to perform correct read/write operations. A GDDR5 system solves this problem by adaptive clock synchronization training. For such multiple clocks synchronization training at controller side this paper proposes two simplified architectures based on: a) Unit-delay incrementer, b) PI (Phase-Interpolator) based PLL (Phase-Locked Loop). Experiments show that the proposed unit-delay architecture consumes only 0.89 mW power and 100 (μm)2area in 65nm which is 16.8 times less power and 35 times less area than other works while power and area consumed in the PI-based PLL architecture depends upon the complexity of the PI itself.

3D ICs are emerging as a promising solution for scalability, power and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes a number of challenges with respect to cost, technological reliability, thermal budget and so forth. Networks-on-chip (NoCs), which is thoroughly investigated in 2D SoCs design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D should be justified with improvements in performance, power or latency. To solve this problem, this paper presents a new simulation framework for 3D NoCs. We established a new Generic Scalable Pseudo Application (GSPA), where user can generate their own scalable pseudo applications. We have also integrated the state-of-the-art benchmarks to evaluate the 3D NoC system. In the framework, the 3D NoC with different vertical channel densities (VD) (i.e. number of Through-Silicon-Vias (TSVs)) can be generated according to the preference of users. After the simulation, the power consumption and system performance are evaluated. We have compared 2D NoC architecture with 3D NoC architecture with different VDs. The experimental results show that 3D architectures have significant advantage (Avg. 51%, 44%, 35% for 100%, 50%, 25% VD, respectively) in the aspect of interconnect power delay product in comparison to 2D mesh architecture. The 25% VD architecture is the best choice with 17% advantage over full connection (100% VD) 3D NoC architecture in the aspect of Figure of Merit which takes area and TSV connection yield into account among all the experiments for the given constrains.

Today industry is moving towards Multi-Processor Systems on Chip (MPSoCs) to take advantage of available parallelism. But common bus architectures for MPSoCs are not suitable as communication infrastructures, due to significant reduction in system throughput. To solve this problem, many Networks-on-Chip (NoCs) architectures have been proposed and analyzed extensively with respect to latency, area and power. The congestion control in NoCs for best-effort communication has gained importance among designers because of the increasing traffic load demand. This paper presents a fast congestion-aware flow control mechanism for ID-Based NoCs with best-effort communication. The proposed method utilizes the combination of local and global control mechanisms, i.e. congestion information at the local node, where the congestion occurs, provides expected injection rates to the corresponding traffic sources. The experimental results indicate that this method can achieve approximately the same network throughput for different traffic scenarios (Hot Spot, Bit Complement and All2One). This method is at least 76% faster than the standard back-pressure mechanism in informing the sending source about the congestion problem in the network (Congestion-Aware Time). The method also shows at least 35% latency improvement (depending upon traffic scenarios) compared to standard back-pressure mechanism.

Besides foundry facilities, Computer-Aided Design (CAD) tools are also required to move microsystems from research prototypes to an industrial market. Currently available CAD tools need extensions before they can be used for the automated design of micromachined devices. This paper presents a low cost access to microsystem technology (MST), applied by the CMP service, and based on the use of existing microelectronics production lines, with additional post-processing for microsystem specific 2D and 3D structures, and a global CAD approach for the design and simulation of microsystems applied to currently available commercial CAD tools, e.g. Mentor Framework, in order t o ensure a continuous flow from the design to the manufacturing.