EDBT 2026 Demo / reviewers in the wild / expert
De-Yu Kao
dblp:13/3420
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
buffer insertion |
0.0 | 1 | 1996 | Performance driven bus buffer insertion · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996 |
Electronic design automation
physical design |
0.0 | 1 | 1996 | Performance driven bus buffer insertion · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996 |
Electronic design automation › physical design › timing optimization
propagation delay optimization |
0.0 | 1 | 1996 | Performance driven bus buffer insertion · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996 |
Electronic design automation › physical design
timing optimization |
0.0 | 1 | 1996 | Performance driven bus buffer insertion · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996 |
Methods — techniques the papers use, named apart from their topics
heuristic algorithm · 0.0buffer sizing · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Performance driven bus buffer insertionabstractIn this paper, we propose a heuristic algorithm for a given topology of a multisource multisink bus to reduce the signal delay time. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. When compared with the traditional method of source driver sizing, experiments show up to 7.2%, 20.7%, and 29.6% improvement in delay for 2.0, 0.5, and 0.3 /spl mu/m technologies, respectively. Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 1995 | Performance driven multiple-source bus synthesis using buffer insertionabstractNo abstract available. Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin |
ASP-DAC | 2 |