Systems of different types of agents coupled with high-order interactions can emerge complex synchronization patterns. This article presents an analysis framework to study the group synchronization of heterogeneous multiagent systems with hierarchical structure and directed interactions of arbitrary order. First, directed hypergraph is introduced to describe the arbitrary-order interactions among the agents. Then, to explore the possible group synchronization patterns, the agent partition methods commonly used in dyadic graphs are extended to the directed hypergraph. Meanwhile, to verify the admissibility of the group synchronization patterns, two equitable partition types of agent partition are defined from the perspective of hyperedge partition. Next, using the simultaneous block diagonalization method, the stability problem of the group synchronous solution is decoupled into several independent subblocks. These subblocks are associated with the perturbations along and transverse to the synchronous manifold, with transverse subblocks related to loss of synchronization. Therefore, the stability of the group synchronous solution can be investigated by evaluating the stability of each transverse subblock via the master stability function method, thus significantly reducing the stability calculation complexity. Finally, the effectiveness of the analysis framework is illustrated via the simulation.

A novel non-volatile 1-bit binary comparator based on pure memristors and an 8-bit comparator based on 1T1M (1 transistor per memristor) crossbar array are proposed in this paper. The proposed comparator is sneak-path free and has short delays. It can be extended to an arbitrary N-bit comparator with 7N memristors and 7N transistors. The worst case input-to-output delay is 4.8ns. A 64-bit comparator shows an maximum power dissipation of 9.38mW at 1.25GHz. Besides, the proposed comparator is nonvolatile and can combine computation with memory. The feasibility and correctness of our design is verified by HSPICE with VTEAM model.

In this paper, we propose a novel Verilog-A based memristor model for effective simulation and application. Our proposed model captures desired nonlinear characteristics using voltage-based state control. This model is flexible and accurate, it can exhibit all the behaviors of HP memristive device and a general class memristive device resistive random access memory which is important in logic and memory design. Furthermore, we can antiserially connect two proposed models to capture the ideal I-V characteristics of complementary resistive switch (CRS). We demonstrate that our proposed CRS model-based crossbar arrays can significantly reduce sneak path currents with high noise margin compared to traditional memristor-based architectures.