Demo Data from EDBT 2026 / reviewers in the wild / expert
P. C. Capon
dblp:13/3537
· DBLP profile ↗
4ranked-venue papers
1as first author
0since 2021 · last 1985
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 2Applied, interdisciplinary, general and emerging computing · 2 · 1 first-authorSystems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 44% Parallel and multicore computing · 44% Interconnection networks and networks-on-chip · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › parallel architecture
parallel vector processing |
0.0 | 1 | 1985 | MU6V: A Parallel Vector Processing System · ISCA 1985 |
Processor architecture and microarchitecture
vector processing |
0.0 | 1 | 1985 | MU6V: A Parallel Vector Processing System · ISCA 1985 |
Interconnection networks and networks-on-chip
interprocessor communication |
0.0 | 1 | 1985 | MU6V: A Parallel Vector Processing System · ISCA 1985 |
Methods — techniques the papers use, named apart from their topics
emulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1985 | MU6V: A Parallel Vector Processing SystemabstractMU6V is a parallel vector processing system in which a linear set of processors, each capable of both vector and scalar operations, is interconnected by a common communication highway.Memory is fully distributed among the processors and interprocessor communication occurs by means of global broadcasts controlled in hardware by a data driven synchronization mechanism.A prototype model based on 68000 microprocessors, in which vector orders are emulated as "extracodes", has been constructed.A host machine provides a software support environment and a run-time system in the prototype provides diagnostic information.Programming language features have been designed to exploit this configuration and an example algorithm is presented. Roland N. Ibbett, P. C. Capon, Nigel P. Topham |
ISCA | 2 |
| 1979 | The Portable Compiling Systems of MUSSabstractAbstract Portability of MUSS compilers is achieved by using an abstract machine model concept. Two different abstract models, both suited for multi‐language multi‐machine usage, have been developed and evaluated. These models differ mainly in the level of interface to the compiler. The form of these models and the performance of two compilers, each using both models, are presented. Howard Barringer, P. C. Capon, R. Philips |
Softw. Pract. Exp. | 2 |
| 1972 | The MU5 compiler target language and autocodeabstractIn this paper the design of the software implementation language for the MU5 machine is considered. This has two representations, the written language, MU5 Autocode, and the parametric compiler target language (CTL). P. C. Capon, Derrick Morris, Jeffrey S. Rohl, I. R. Wilson |
Comput. J. | 1 |
| 1970 | A System Program GeneratorabstractThis paper describes a self expanding program generator aimed at the general area of system programming. A syntax directed scan is used for statement recognition. The set of statements is extended by additions to the syntax tables. Derrick Morris, I. R. Wilson, P. C. Capon |
Comput. J. | 3 |