Demo Data from EDBT 2026 / reviewers in the wild / expert
Daniel E. Farmer
dblp:13/3834 · also D. E. Farmer
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1975
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 76% Integrated circuit design · 24% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
fault-detection experiment |
0.0 | 2 | 1975 | Fault-Detection Experiments for Parallel-Decomposable Sequential Machines · IEEE Trans. Computers 1975 Algorithms for Designing Fault-Detection Experiments ror Sequential Machines · IEEE Trans. Computers 1973 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1975 | An Algebraic Method for Designing Multivalued Logic Circuits using Principally Binary Components · IEEE Trans. Computers 1975 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1975 | Fault-Detection Experiments for Parallel-Decomposable Sequential Machines · IEEE Trans. Computers 1975 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1975 | An Algebraic Method for Designing Multivalued Logic Circuits using Principally Binary Components · IEEE Trans. Computers 1975 |
Electronic design automation › logic synthesis › logic minimization
multiple-valued logic minimization |
0.0 | 1 | 1975 | An Algebraic Method for Designing Multivalued Logic Circuits using Principally Binary Components · IEEE Trans. Computers 1975 |
Integrated circuit design › digital circuit design
multivalued logic circuit |
0.0 | 1 | 1975 | An Algebraic Method for Designing Multivalued Logic Circuits using Principally Binary Components · IEEE Trans. Computers 1975 |
Electronic design automation › hardware verification and test
fault detection |
0.0 | 1 | 1973 | Algorithms for Designing Fault-Detection Experiments ror Sequential Machines · IEEE Trans. Computers 1973 |
Electronic design automation › hardware verification and test
sequential circuit testing |
0.0 | 1 | 1973 | Algorithms for Designing Fault-Detection Experiments ror Sequential Machines · IEEE Trans. Computers 1973 |
Methods — techniques the papers use, named apart from their topics
state identification · 0.0prime implicant generation · 0.0locating sequence · 0.0covering · 0.0algebraic reduction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1975 | An Algebraic Method for Designing Multivalued Logic Circuits using Principally Binary ComponentsabstractAlgebraic reduction procedures for multivalued logic functions based upon a principally binary circuit realization are presented. The procedures given are also applicable to literal gate realizations employing compound literals. The prime implicant generation and covering problems are treated in detail. It is shown that the selected cover must be iteratively examined for possible reduction at each decision point of the covering process. This reduction is achieved by the elimination of unnecessary nonadjacencies. J. E. Birk, Daniel E. Farmer |
IEEE Trans. Computers | 2 |
| 1975 | Fault-Detection Experiments for Parallel-Decomposable Sequential MachinesabstractMethods are presented for designing fault-detection experiments for sequential machines which are realized as parallel connections of simpler component machines. The outputs of these components are assumed to be inaccessible for measurement but it is shown that knowledge of the structure can be utilized to design simpler experiments. The procedure is based upon placing all components but one in a fixed reference state prior to measuring input/output sequences for this one component in order to deduce its state table. This means that the only measurable transitions are those which return the other components to their reference states. Such transitions are made in response to application of restricted input sequences and it is necessary that the state table be deduced from such a set of observations. Daniel E. Farmer |
IEEE Trans. Computers | 2 |
| 1973 | Algorithms for Designing Fault-Detection Experiments ror Sequential MachinesabstractIn this paper we present algorithms for designing fault-detection experiments for sequential machines with special emphasis on the case in which the machine does not possess a distinguishing sequence. The length of an experiment is reduced through: 1) identifying each state with its own unique input/output set rather than using a common set for all states; 2) utilizing overlapping of the required input/output sequences so that a portion of the experiment serves more than one purpose; and 3) verifying the reference condition in which the machine is placed at many points in the experiment by as short a locating sequence as possible. Important distinctions are made between locating sequences of the type introduced in previous work and those defined and used here. Daniel E. Farmer |
IEEE Trans. Computers | 1 |