Brain-Computer Interfaces (BCIs) have the potential to restore motion for patients suffering from spinal cord injuries. Making such systems embedded, or even implantable, imposes strict low power constraints. Feature extraction, which transforms brain signals into intermediate representations before decoding motor intent, is typically the most compute intensive step. In this work, we introduce ALIFE-BCI, an Adaptive Quality Feature Extractor (AQFE), based on a Continuous Wavelet Transform (CWT) that captures the signal dynamics in both the time and frequency domains. The system is optimized with a top-down approach: (i) At the algorithmic level, it implements a piecewise linear approximation of the CWT that allows real-time energy-accuracy trade-offs. (ii) At the architectural level, memory reuse and parallelism are used to balance area and compute performance. (iii) At the circuit level, low-power techniques are used in a 22 nm FDSOI technology physical implementation flow. Three variants, with different levels of parallelism, are explored to extract 960 features at a rate of 10 Hz for a BCI motor application. The optimal variant, with an area of only 0.061 mm2, achieves 0.27 μW/feature at maximum quality, and 0.13 μW/feature at minimum quality, resulting in 8× lower power than existing digital solutions. Combined, these characteristics make the system well-suited for ultra-low-power implantable BCI decoders.

In clinical trials, brain signal decoders combined with spinal stimulation have shown to be a promising means to restore mobility to paraplegic and tetraplegic patients. To make this technology available for home use, the complex brain signal decoding must be performed using a low-power, portable battery operated system. This case study shows how the decoding algorithm for a Brain-Computer Interface (BCI) system was ported to an embedded platform, resulting in an over 25 x power reduction, compared to the previous implementation, while respecting real-time and accuracy constraints.

The explosion of IoT and wearable devices determined a rising attention toward energy harvesting as source for powering these systems. In this context, many applications cannot afford the presence of a battery because of size, weight, and cost issues. Therefore, due to the intermittent nature of ambient energy sources, these systems must be able to save and restore their state, in order to guarantee progress across power interruptions. In this work, we propose a specialized backup/restore controller that dynamically tracks the memory accesses during the execution of the program. The controller then commits the changes to a snapshot in a nonvolatile memory (NVM) when a power failure is detected. Our approach does not require complex hybrid memories and can be implemented with standard components. Results on a set of benchmarks show an average 8× reduction in backup size. Thanks to our dedicated controller, the backup time is further reduced by more than 100×, with an area and power overhead of only 0.4% and 0.8%, respectively, with respect to a low-end IoT node.

Achieving the lowest possible operating voltage is needed to minimize the power consumption of a circuit but also to increase its reliability w.r.t hardware errors. An in-situ technique to estimate and reduce the design margins of a circuit is presented which significantly minimizes the operating voltage and tracks it during run-time operation of a circuit without failure. A DSP core embedding this technique has been fabricated and measured. Its Vminhas been estimated within +3.5%/-2.5% at nominal clock frequency (1600MHz), thus reducing by 19% its energy per operation.

In this paper we propose to give an overview of fine-grain design techniques we demontrated past years in our lab for power reduction in complex SoCs. Those works are based on Globally Asynchronous and Locally Synchronous systems in which each IP is an independent voltage and frequency domain. After having proposed some simple DFS architectures based on GALS architectures in 130nm technology, we extended our works to fine-grain Dynamic Voltage and Frequency Scaling architectures to reduce dynamic and static power reduction at 65 nm node. Furthermore, considering 32 nm deep submicron technologies, we demonstrated an Adaptive Voltage and Frequency architecture to compensate for in-die PVT variations. Area overhead and power reduction results are discussed all along the paper.

The emerging SOI technologies provide an increased body bias range compared to traditional bulk technologies, opening new opportunities. From the power management perspective, a new degree of freedom is added to the supply voltage and clock frequency variation, increasing the complexity of the power optimization problem. In this paper, a method is proposed to manage the power consumed in an FD-SOI circuit through supply and body bias voltages, and clock frequency variation. Results for a Digital Signal Processor in STMicroelectronics 28nm FD-SOI technology show that the power reduction ratio can reach 17%.

Shadow-scan solutions are proposed in order to facilitate the implementation of faster scan flip-flops (FFs) with optional support for in-situ slack-time monitoring. These solutions can be applied to system FFs placed at the end of timing-critical paths while standard-scan cells are deployed in the rest of the system. Automated scan stitching and automated test pattern generation (ATPG) can be performed transparently with commercial tools. The generated test patterns cover not only the mission logic but also the monitoring infrastructure. The latency of itc'99 benchmark circuits could be reduced with up to 10% while the stuck-at fault coverage (FC) was preserved as compared to circuit versions with full standard-scan design. Limited variations in the number of test patterns were observed when support for in-situ slack-time monitoring was provided.

In-situ slack-time monitoring may be used to enable ambitious power management policies under circuit wear-out and dynamic temperature and supply voltage variations. Given a limited hardware budget, it becomes crucial to be able to select the most appropriate places for in-situ slack-time monitoring. Here, two metrics are proposed to guide the selection of a set of flip-flops (FFs) for in-situ slack-time monitoring. The goal of these metrics is to maximize the ratio of clock cycles with at least one monitor activated and the number of activated monitors per clock cycle. The activation probability of a monitor is evaluated with the help of timing simulations as the probability that signals are propagated along the monitored timing-critical paths. It is shown that in-situ slack-time monitors with detection windows correlated to the minimum slack-time of the monitored timing-critical paths can provide better results than similar monitors with a constant detection window for the same impact on the circuit latency.

3D stacking is currently seen as a breakthrough technology for improving bandwidth and energy efficiency in multi-core architectures. The expectation is to solve major issues such as external memory pressure and latency while maintaining reasonable power consumption. In this paper, we show some advances in this field of research, starting with memory interface solutions as WIDEIO experience on a real chip for solving DRAM accesses issue. We explain the integration of a 512-bit memory interface in a Network-on-Chip multi-core framework and we show the performance we can achieve, these results being based on a 65nm prototype integrating 10µm diameter Through Silicon Vias. We then present the potentiality of new fine grain 3D stacking technology for power-efficient memory hierarchy. We expose an innovative 3D stacked multi-cache strategy aimed at lowering memory latency and external memory bandwidth requirements and thus demonstrating the efficiency of 3D stacking to rethink architectures for obtaining unequalled performances in power efficiency.

3D stacking has been viewed as a breakthrough solution for increasing performance in multi-core architectures. The hope is to solve some of the main issues in current multi-core architectures: external memory pressure and latency; I/O bottleneck; communication power consumption. In this paper, some advances of this field of research are shown, starting with a WIDEIO experience on a real chip for solving DRAM accesses issue. The integration of a 512 bit-width bus is demonstrated in a Network-on-Chip (NoC) multi-core framework and the resulting performance based on a 65nm prototype with 10μm diameter Through Silicon Vias (TSV). The potentiality of 3D scaling thanks to 3D asynchronous Network-on-Chip implementation is then shown. Finally, an innovative 3D stacked distributed cache strategy aimed at lowering memory latency and external memory bandwidth requirements is presented. This new memory partitioning demonstrates the efficiency of 3D stacking to rethink architectures for addressing multi-core scaling challenges.

New fine-grained 3D cache architectures have been recently proposed to embed more memory on-chip and thus reduce off-chip memory accesses. These 3D architectures provide a high access bandwidth thanks to wide vertical links. In this paper, we analyze the performances of such caches in a manycore context. We first propose to improve the microarchitecture of an existing 3D non uniform cache architecture. Then we evaluate the impact of the granularity (number of tiles) of this 3D cache on an existing multicore architecture executing high performance computing workloads. We show that the granularity of the 3D cache can affect the performances by a factor of 300%. We also evaluate the impact of the vertical links granularity (number of vertical 3D NoC links) on performances and show that a high number of these links is necessary to achieve the best performanes. Finally, we compare this fine-grained architecture to a memory using a Wide IO interface and show that the latter is less efficient in a manycore context.

The distribution of a synchronous clock in system-on-chip (SoC) has become a problem, because of wire length and process variation. Novel approaches such as the globally asynchronous, locally synchronous try to solve this issue by partitioning the SoC into isolated synchronous islands. This paper describes the bisynchronous FIFO used on the DSPIN network-on-chip capable to interface systems working with different clock signals (frequency and/or phase). Its interfaces are synchronous and its architecture is scalable and synthesizable in synchronous standard cells. The metastability situations and its latency are analyzed. Its throughput, maximum frequency, and area are evaluated in function of the FIFO depth.