Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. The three methods are complementary in that they are designed to target different process variation conditions that occur in practice. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Timing analysis results in the face of statistical temperature and Vddvariations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results

Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first-order delay model that takes into account both correlated and independent randomness is proposed. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivity of all timing quantities to each of the sources of variation is available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature, which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in computer time, the probability of each edge or node of the timing graph being critical is computed. Numerical results are presented on industrial application-specified integrated circuit (ASIC) chips with over two million logic gates, and statistical timing results are compared to exhaustive corner analysis on a chip design whose hardware showed early mode timing violations

Process variations - which affect critical electrical parameters and lead to both random and systematic changes in circuit performance - have always posed significant challenges to semiconductor design. In the past, within-die process variation was relatively small, and methods such as corner-based analysis were sufficient. This allowed timing analysis tools to calculate delays, slew times, coupling and power in a straightforward way. Today, the International Technology Roadmap for Semiconductors suggests that the semiconductor industry's historical ability to control process variations is under siege, for both devices and interconnects. As statistical variation increases, will corner-casing lead to too much conservatism, and hence a requirement for new statistical timing and noise analysis tools? In other words, is the design flow inevitably moving to "delay is no longer a number; it's a distribution"? Or are the urgency and the advantages of statistical timing analysis overstated.

Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivities of all timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the timing graph being critical is computed. Numerical results are presented on industrial ASIC chips with over two million logic gates.

Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Across-the-chip variability continues to be accommodated by EinsTimer's "Linear Combination of Delay (LCD)" mode. Timing analysis results in the face of statistical temperature and Vdd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results.

Almost by definition, well-tuned digital circuits have a large number of equally critical paths, which form a so-called "wall" in the slack histogram. However, by the time the design has been through manufacturing, many uncertainties cause these carefully aligned delays to spread out. Inaccuracies in parasitic predictions, clock slew, model-to-hardware correlation, static timing assumptions and manufacturing variations all cause the performance to vary from prediction. Simple statistical principles tell us that the variation of the limiting slack is larger when the height of the wall is greater.Although the wall may be the optimum solution if the static timing predictions were perfect, in the presence of uncertainty in timing and manufacturing, it may no longer be the best choice. The application of formal mathematical optimization in transistor sizing increases the height of the wall, thus exacerbating the problem. There is also a practical matter that schematic restructuring downstream in the design methodology is easier to conceive when there are fewer equally critical paths. This paper describes a method that gives formal mathematical optimizers the incentive to avoid the wall of equally critical paths, while giving up as little as possible in nominal performance. Surprisingly, such a formulation reduces the degeneracy of the optimization problem and can render the optimizer more effective. This "uncertainty-aware" mode has been implemented and applied to several high-performance microprocessor macros. Numerical results are included.

This paper surveys the state-of-the-art in continuous nonlinear optimization and makes the case that due to tremendous recent progress, larger and more complex problems can be solved than previously thought possible. The two basic paradigms, trust-region and line-search methods, are briefly described. In addition, various nonlinear optimization techniques are reviewed. The application of these nonlinear optimization methods to circuit sizing is presented by describing a pair of circuit sizing tools, one for dynamic tuning and one for tuning based on static timing analysis. Particular emphasis has been given to the customization of nonlinear optimization to the circuit sizing application.

Noise can cause digital circuits to switch incorrectly, producing spurious results. It can also have adverse power, timing and reliability effects. Dynamic logic is particularly susceptible to charge-sharing and coupling noise. Thus, the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semi-infinite constraints in the time-domain. Semi-infinite problems are generally harder to solve than standard nonlinear optimization problems. Moreover, the number of noise constraints can potentially be very large. This paper describes a novel and practical method for incorporating realistic noise considerations during automatic circuit optimization by representing semi-infinite constraints as ordinary equality constraints involving time integrals. Using an augmented Lagrangian optimization merit function, the adjoint method is applied to compute all the gradients required for optimization in a single adjoint analysis, no matter how many noise measurements are considered and irrespective of the dimensionality of the problem. Thus, for the first time, a method is described to practically accommodate a large number of noise considerations during circuit optimization. The technique has been applied to optimization using time-domain simulation, but could be applied in the future to optimization on a static-timing basis. Numerical results are presented.

Article Free Access Share on Gradient-based optimization of custom circuits using a static-timing formulation Authors: A. R. Conn IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile , I. M. Elfadel IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile , W. W. Molzen IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile , P. R. O'Brien IBM Electronic Design Automation, 11400 Burnet Road, M. S. 9460, Austin, TX IBM Electronic Design Automation, 11400 Burnet Road, M. S. 9460, Austin, TXView Profile , P. N. Strenski IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile , C. Visweswariah IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile , C. B. Whan IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NY IBM Thomas J. Watson Research Center, Route 134 and Taconic, Yorktown Heights, NYView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 452–459https://doi.org/10.1145/309847.309979Published:01 June 1999Publication History 29citation367DownloadsMetricsTotal Citations29Total Downloads367Last 12 Months21Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Static circuit optimization implies sizing of transistors and wires on a static timing basis, taking into account all paths through a circuit. Previous methods of formulating static circuit optimization produced problem statements that are very large and contain inherent redundancy and degeneracy. In this paper, a method of manipulating the timing formulation is presented which produces a dramatically more compact optimization problem, and reduces redundancy and degeneracy. The circuit optimization is therefore more efficient and effective. Numerical results to demonstrate these improvements are presented.

Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability effects. Dynamic logic is particularly susceptible to charge-sharing and coupling noise. Thus the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semi-infinite constraints. In addition, the number of signals to be checked and the number of sub-intervals of time during which the checking must be performed can potentially be very large. Thus, the practical incorporation of noise constraints during circuit optimization is a hitherto unsolved problem. This paper

Automating the transistor and wire-sizing process is an important step toward being able to rapidly design high-performance, custom circuits. This paper presents a circuit optimization tool that automates the tuning task by means of state-of-the-art nonlinear optimization. It makes use of a fast circuit simulator and a general-purpose nonlinear optimization package. It includes minimax and power optimization, simultaneous transistor and wire tuning, general choices of objective functions and constraints, and recovery from nonworking circuits. In addition, the tool makes use of designer-friendly interfaces that automate the specification of the optimization task, the running of the optimizer, and the back-annotation of the results of optimization onto the circuit schematic. Particularly for large circuits, gradient computation is usually the bottleneck in the optimization procedure. In addition to traditional adjoint and direct methods, we use a technique called the adjoint Lagrangian method, which computes all the gradients necessary for one iteration of optimization in a single adjoint analysis. This paper describes the algorithms and the environment in which they are used and presents extensive circuit optimization results. A circuit with 6900 transistors, 4128 tunable transistors, and 60 independent parameters was optimized in about 108 min of CPU time on an IBM RISC/System 6000, model 590.

The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable parameters, the direct method is used to repeatedly solve the associated sensitivity circuit to obtain all the necessary gradients. Likewise, when the parameters outnumber the measurements, the adjoint method is employed to solve the adjoint circuit repeatedly for each measurement to compute the sensitivities. In this paper we propose the adjoint Lagrangian method, which computes all the gradients necessary for augmented-Lagrangian-based optimization in a single adjoint analysis. After the nominal simulation of the circuit has been carried out, the gradients of the merit function are expressed as the gradients of a weighted sum of circuit measurements. The weights are dependent on the nominal solution and on optimizer quantities such as Lagrange multipliers. By suitably choosing the excitations of the adjoint circuit, the gradients of the merit function are computed via a single adjoint analysis, irrespective of the number of measurements and the number of parameters of the optimization. This procedure requires close integration between the nonlinear optimization software and the circuit simulation program.

This paper studies the confidence with which power can be estimated at various levels of design abstraction. We report the results of experiments designed to evaluate and identify the sources of inaccuracies in gate-level power estimation. In particular, we are interested in power estimation during logic synthesis. Factors that may invalidate or diminish the accuracy of pourer estimates include optimization, technology mapping, transistor sizing, physical design, and choice of input stimuli.

Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design high-performance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses LANCELOT, a large-scale nonlinear optimization package with an augmented Lagrangian formulation. Simple bounds are handled explicitly and trust region methods are applied to minimize a composite objective function. In the inner loop of the optimization, the fast circuit simulator SPECS is used to evaluate the circuit. SPECS is unique in its ability to efficiently provide time-domain sensitivities, thereby enabling gradient-based optimization. Both the adjoint and direct methods of sensitivity computation have been implemented in SPECS. To assist the user, interfaces in the Cadence and SLED design systems have been constructed.

Article Free Access Share on Incremental event-driven simulation of digital FET circuits Authors: Chandramouli Visweswariah View Profile , Jalal A. Wehbeh View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 737–741https://doi.org/10.1145/157485.165111Published:01 July 1993Publication History 8citation197DownloadsMetricsTotal Citations8Total Downloads197Last 12 Months4Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A unified multilevel mixed-mode simulation capability for mixed analog/digital integrated circuits is described. First, a methodology for describing arbitrary analog or mixed analog/digital blocks at the behavioral level is proposed. In order to verify such models, a verification tool has been developed. The tools modgens and modgenz convert transfer functions H(s) and H(z), respectively, into state space representations in the time domain and generate behavioral models. Thus, the methodology allows digital, analog, and mixed analog/digital subcircuits to be described at various levels. While the analog portions of the circuit are simulated with high accuracy, the digital portions can be simulated in various models. Simulation is event-driven. For the behavioral analog models, block elimination with unique reordering and pivoting techniques are used to accommodate state variables. This capability has been integrated into the MOTIS3 design verification system. The simulation of representative mixed analog/digital simulation examples is described.>

High-performance logtc circuitry for mairlfrarne computers IS most commonly tmpltrnerttcd trt the btpolar emitter-coupled logtc (E CL) faintly.BtC,~~OS circuits are becoming increastng[y common tJt dlgztal applications.The .wmulaiton of such circuits twih a general pUrpOSe CirCUl~alla/,~SIS tOO[ 1S Z)

A simulation methodology for the nonlinear transient analysis of electrical circuits is described. Equations are formulated on the tree/link basis. All branch and node variables are modeling to be piecewise approximate in time. Electronic devices are represented by empirical table models of I-V characteristics. The table models may be built at various levels of precision, and concomitant accuracy levels are reflected in the simulation results. Simulation accuracy may be varied on a branch-by-branch basis or global basis, this permitting the user to distribute computer resources in a meaningful manner. The simulation algorithm is event driven and fully exploits temporal sparsity in the underlying circuit equations. Mechanisms for dealing with steady-state situations and stiff circuits have been investigated. A prototype simulator, SPECS, has been developed and tested on large industrial integrated circuits. It has proven to be a reliable and efficient tool in the analysis of digital and mixed circuits.>

The incorporation of inductors in a piecewise approximate circuit simulator, enhancing the generality of such a tool, is presented. Most approximate timing simulators preclude inductors from the underlying circuit. Conventional simulators allow inductive effects, but are too inefficient to simulate very large circuits. The formulation presented allows the event-driven simulation of circuits containing inductors, capacitors and general nonlinear elements. The event processing algorithm is based on the conservation of flux and energy. The implementation was tested in a prototype addition to the SPECS simulation environment. In addition, the theory behind the incorporation of mutual inductors is presented. A few benchmarks were run to confirm the veracity of the model. Research into the automatic, dynamic determination of the optimum current resolution would cause the tool to be more efficient, as well as relieve the designer of choosing a current resolution for the inductors in the circuit.>

Conventional circuit simulation methods are inflexible and slow, especially for large circuits. Piecewise approximate circuit simulation, an alternative that can be more efficient and allows variable accuracy in the simulation process, is discussed. Thus, the tradeoff between accuracy and CPU time is in the hands of the user. SPECS (simulation program for electronic circuits and systems) is the prototype implementation of a piecewise approximate, tree/link based, event driven, variable accuracy circuit simulation algorithm that uses table models for device evaluation. The models can be built at various levels of accuracy, and concomitant levels of precision are reflected in the simulation results. SPECS has been benchmarked on some large, industrial circuits and has proven to be an efficient and reliable simulator. However, it suffers a penalty in run time while simulating stiff circuits, or circuits with a wide range of time constants. The authors present enhanced algorithms used in SPECS to ensure efficient steady-state computation for stiff circuits.>