With the continuous maturity of Internet of Things (IoT) technology, it has begun to be frequently used in all walks of life to improve people's work efficiency and living standards. The wide use of IoT in the medical field makes it convenient for patients to obtain medical services, and also enables doctors to obtain patients' physical conditions more timely and accurately, so as to formulate more efficient treatment plans. However, when people enjoy the convenience of medical IoT, how to ensure the security of communication and privacy of patients are all problems that cannot be ignored. In order to achieve secure access the network, this paper proposes an anonymous password authenticated key exchange protocol for medical Internet of Things (PAMI), where only a low-entropy password is required to realize the mutual authentication between medical device and telemedicine server, so as to negotiate a high-entropy session key. The security of PAMI is formally proved under the standard model, and the experiment based performance comparison demonstrates that it is more efficient than the existing similar schemes.

Vehicle to Vehicle (V2V) communication opens a new way to make vehicles directly communicate with each other, providing faster responses for time-sensitive tasks than cellular networks. Effective V2V routing protocols are essential yet challenging, as the high dynamic road environment makes communication easy to break. Many prediction methods proposed in the existing protocols to address this issue are either flawed or have a poor effect. In this paper, to cope with the two aspects of the problems that cause communication interrupt, i.e., link breaks and route quality degradation, we design an acceleration-based trajectory prediction algorithm to estimate the link lifetime, and a machine learning model to predict route quality. Based on the prediction algorithms, we propose PQR, a Prediction-supported Quality-aware Routing protocol, which can proactively switch to a better route before the current link breaks or the route quality degrades. Especially, considering the limitations of the current routing protocols, we elaborate a new hybrid routing protocol that integrates the topology-based method and location-based method to achieve instant communication. Simulation results show that PQR outperforms the existing protocols in Packet Delivery Ratio (PDR), Roundtrip Time (RTT), and Normalized Routing Overhead (NRO). Specifically, we have also implemented a vehicular testbed to demonstrate PQR’s real-world performance, and results show that PQR achieves almost no packet loss with latency less than 10ms during route handoff for topology change.

With the proliferation of users in wireless communication networks and the increase in traffic, heterogeneous networks have emerged. Minimizing the total energy consumption of base stations is an important issue for environmental reasons. Therefore, the concept of a green heterogeneous network was proposed. However, the deployment of a large number of small base stations also poses problems for user management. In order to better improve the decision-making and self-organizing ability of the network, the paper also proposes an user energy consumption prediction model based on Recurrent Neural Network. After that, the article also proposes a power control scheme through a Deep Reinforcement Learning algorithm with Long Short-Term Memory to improve the quality of user service. Finally, a joint optimization scheme of network power control and user management is realized. The experimental results show that the joint optimization effect using this method can converge to better solution and reduce energy consumption compared with traditional deep reinforcement learning.

Energy efficient routers are important and promising devices in the roadmap toward green networking. In this paper, we explore this topic with a traffic aware design that can automatically adapt the router's energy consumption to the network traffic in real time with transitions at the scale from microseconds to nanoseconds. In this paper, we make three contributions. First, we propose an energy efficient router architecture using frequency scaling, which is extended from the contemporary line card architecture of the router. Second, we prototype our architecture on a gigabit NetFPGA platform, which extends a router design on that platform to dynamically work at six frequencies. Then, we discuss the implementation in detail and present a per-packet-based power consumption model from real-world measurements. Third, we further propose four algorithms, which efficiently and automatically adapt power grades under the methodology of periodical and threshold-based scaling. Our experiments are carried out on two platforms, a NetFPGA prototype for feasible scenarios and a simulator for other scenarios in excess of the NetFPGA port limit with parameters synthetically generated to the real-world measurement. Experimental results show that approximately 25% power can be saved with our architecture and algorithms. Conclusions are also given to summarize our findings.

Abstract In Long Term Evolution Advanced networks with Type I in‐band half‐duplex decode‐and‐forward relay nodes, proportional fair (PF) resource allocation is aiming at guaranteeing two‐hop match and optimising global proportional fairness. The two‐hop match is defined as equal data rates in the access links and the corresponding backhaul links. The global proportional fairness is between all the user equipments served by the evolved nodes B and the relay nodes. Existing centralised schemes achieve these targets at the cost of enormous channel state information (CSI) exchange. Existing distributed schemes focus on resource partitioning and employ a traditional single‐hop PF scheduling algorithm in access links, with less CSI exchange. The traditional PF scheduling algorithm maximises single‐hop proportional fairness between the data rates in the access links rather than two‐hop proportional fairness between the end‐to‐end data rates in the two hops. In order to reduce CSI exchange and at the same time to maximise the two‐hop proportional fairness, a distributed two‐hop PF resource allocation scheme is proposed. The proposed scheme includes two‐hop PF resource scheduling algorithms and adaptive resource partitioning algorithms, applied in different two‐hop transmission protocols. Simulation results demonstrate the proposed scheme is better than the existing distributed schemes in obtaining better proportional fairness and larger cell‐edge user equipment throughputs. Copyright © 2014 John Wiley & Sons, Ltd.

Abstract The cloud storage service has been widely used in daily life because of its convenience. However, the service frequently suffers confidentiality problems. To address this problem, some efforts have been made on keyword search over encrypted data schemes. For instance, the chaotic‐based keyword search scheme over encrypted data has been proposed recently. However, the scheme just only support single‐ keyword search each time, which severely limits its utilization in cloud storage. This article proposes a novel chaotic‐based time‐aware multi‐keyword search scheme with designated server. Inner product similarity is adopted in our scheme to realize multiple keyword search and remove the constraint of single‐keyword search each time. Timed‐release encryption is integrated into the proposed scheme at the same time, which enables the data sender to specify the time when the cloud servers can search the encrypted data. Analysis indicates that our scheme not only can counter off‐line guessing attacks to the ciphertext and trapdoor, but also supports ranked search with a reasonable computational cost. Copyright © 2015 John Wiley & Sons, Ltd.

Modular multiplication is a core operation in all public key based cryptosystems. The performance of these cryptosystems can be enhanced substantially by incorporating an optimized modular multiplier. This paper presents serial and parallel radix-4 modular multipliers based on interleaved multiplication algorithm and Montgomery power laddering technique. A serial radix-4 interleaved modular multiplier provides 50% reduction in the required clock cycles. In addition to the reduction in clock cycles, a parallel modular multiplier maintains a critical path delay comparable to the bit serial interleaved multipliers. The proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. The serial radix-4 multiplier computes a 256-bit modular multiplication in 1.3μs, occupies 3.9K LUTs, and runs at 96 MHz. The parallel radix-4 multiplier takes 0.77μs, occupies 5.3K LUTs, and runs at 166 MHz. The results show that the parallel radix-4 modular multiplier provides 62% and 49% speed-up over the corresponding bit serial and bit parallel versions, respectively. Thus, these designs are suitable to accelerate modular multiplication in many cryptographic processors.

Energy efficiency is now a significant concern for network infrastructure and next-generation network devices are expected to embed advanced power management capabilities. However, the effective exploitation of advanced power management capabilities in network devices which adaptively meet network load and operational constraints is still a considerable challenge due to the stochastic properties of the actual traffic load. In this paper, a statistical optimal local control policy for dynamic control of power state configurations according to the actual traffic load is proposed to minimize the power consumption while meeting the performance constraints. The packet-level statistical features of network traffic load is modeled as a first-order Markov chain and the dynamic power state selection problem is formulated as a Markov decision process, which can be solved using dynamic programming. In addition, we discuss the possibility of implementing the proposed scheme in real network devices, and design a case study in an NetFPGA frequency scaled router. Simulation results are presented to show the effectiveness of the proposed scheme.

With the employment of relay nodes (RNs) in Long Term Evolution Advanced (LTE-Advanced) networks, some cell-edge User Equipments (UEs) are served by RNs to improve received signal strength and mitigate interference. In in-band mode, they are allowed to reuse the resources allocated to the UEs connected to the evolved Nodes B (eNBs) in the same cell. Frequency reuse inside a cell can increase the number of available resources per cell and can also produce intra-cell interference. In order to alleviate the detrimental impact of interference and maximise network performance at the same time, we propose an adaptive partial frequency reuse (APFR) scheme, which includes a resource partitioning algorithm and a route selection algorithm. We first formulate the APFR problem into a generalised proportional fairness problem. After getting a mathematical solution, we determine the number of reused resources, and then the resource partitioning and route selection algorithms are derived sequentially. Simulation results show that the proposed APFR scheme can achieved both larger throughput and better fairness than the benchmarking algorithms with different RN transmitting power and various RN positions.

This paper presents radix-4 and radix-8 Booth encoded modular multipliers over general Fpbased on inter-leaved multiplication algorithm. An existing bit serial interleaved multiplication algorithm is modified using radix-4, radix-8 and Booth recoding techniques. The modified radix-4 and radix-8 versions of interleaved multiplication result in 50% and 75% reduction in required number of clock cycles for one modular multiplication over the corresponding bit serial interleaved multipliers, while maintaining a competitive critical path delay. The proposed architectures are implemented in Verilog HDL and synthesized by targeting virtex-6 FPGA platform. Due to an efficient utilization of optimized addition chains available in FPGAs and exploiting the parallelism among operations, the proposed radix-4 and radix-8 multipliers compute one 256 × 256 bit modular multiplication in 1.49μs and 0.93μs respectively, which are 35% and 94% improvement over the corresponding bit serial version. Further, this work also presents a thorough comparison on basis of area, throughput, and area × time per bit value. Which shows that these designs are efficiently optimized for area × time per bit value with a high throughput rate. Thus, these designs are suitable to construct most of the elliptic curve and pairing based cryptographic processors.

Energy efficient routers are a promising step forward in the road-map towards energy efficient networking. In this paper, we use gigabit routers to measure and evaluate the impacts of green technologies in different scenarios. These programmable NetFPGA based routers come with the inbuilt feature of frequency scaling which can reduce the operational frequency of the board by half from 125MHz to 62.5MHz. Router power consumption is compared for standard and low frequency modes with different numbers of activated ports. Perpacket and per-byte energy costs in different cases with different packet sizes are measured and analyzed to evaluate the effects of frequency adjustment. Finally, a simple energy model for real traffic is proposed and evaluated. This paper reveals the internal power usage of a gigabit router at the granularity of packet, and header and payload byte level, and offers the reader a clear understanding of the potential power savings at different operational router frequencies, for different numbers of activated ports, various traffic loads and packet sizes, which would assist the green data center networks.

Deep Packet Inspection (DPI) in Network Intrusion Detection and Prevention Systems (NIDPS) typically involves the matching of packet payloads against attack signatures in the form of fixed strings and regular expressions. As an attack pattern may span multiple IP fragments or TCP segments, accurate DPI requires that the traffic is reassembled prior to analysis of the payload data stream. Although hardware acceleration of the TCP layer, including reassembly, is well known in the form of TCP Offload Engines for Network Interface Cards, only limited research has been conducted into reassembly architectures suited to the particular requirements of DPI systems. The challenging requirements include the tracking and fragment/segment reordering of a potentially very large number of streams in addition to dealing with subtle ambiguities in IP fragmentation and TCP segmentation using target based reassembly or traffic normalization. In this article, the authors present a combined hardware and software architecture which harnesses the resources of the latest FPGA technology to improve on existing research proposals.

String matching is a key technique for network security applications such as network intrusion detection systems and antivirus scanners, where the payload of every packet is inspected against thousands of patterns in real time. As the transmission rate of Internet links is getting higher and higher, the speed of matching engines is required to be faster and faster. Existing deterministic finite automaton (DFA)-based approaches achieve high throughput at the expense of extremely expensive memory cost; therefore, they are not suitable for the scenarios where only limited on-chip memory resources are available. To achieve fast matching speed while controlling memory expense, in this paper, we propose Kangaroo, a compact string matching scheme that scans multiple characters each time by running multiple small-sized finite state machines in parallel. Specifically, Kangaroo processes k consecutive characters mostly in one cycle by accessing k different memories in parallel, where k is a predefined factor that can be tuned based on the requirement of applications. Kangaroo is memory efficient. Experimental evaluations on Snort and ClamAV rule sets show that a tenfold increase in speed can be practically achieved by a single Kangaroo matching engine with a reduced memory cost comparing with the state-of-the-art DFA-based approaches.

Packet classification is used by networking equipment to sort packets into flows by comparing their headers to a list of rules, with packets placed in the flow determined by the matched rule. A flow is used to decide a packet's priority and the manner in which it is processed. Packet classification is a difficult task due to the fact that all packets must be processed at wire speed and rulesets can contain tens of thousands of rules. The contribution of this paper is a hardware accelerator that can classify up to 433 million packets per second when using rulesets containing tens of thousands of rules with a peak power consumption of only 9.03 W when using a Stratix III field-programmable gate array (FPGA). The hardware accelerator uses a modified version of the HyperCuts packet classification algorithm, with a new pre-cutting process used to reduce the amount of memory needed to save the search structure for large rulesets so that it is small enough to fit in the on-chip memory of an FPGA. The modified algorithm also removes the need for floating point division to be performed when classifying a packet, allowing higher clock speeds and thus obtaining higher throughputs.

Network Intrusion Detection Systems (NIDS) make extensive use of regular expressions (regexes) as attack signatures. Such expressions can be handled in hardware using a bit‐parallel (BP) architecture based on the Glushkov non‐deterministic finite automata (NFA). However, many expressions contain constrained {min, max} repetitions which first need to be unrolled so that they can be handled by the standard BP system. Such unrolling often leads to an excessive memory requirement which makes handling of such regexes unfeasible. This study presents a solution, based on the standard BP architecture, which incorporates a counting mechanism that renders unrolling unnecessary. As a result, many regexes, which were previously unsuitable for the standard BP system, can now be efficiently handled. Unlike many other approaches, this architecture is dynamically reconfigurable thanks to its memory, rather than logic, based engine. This is important as NIDS rule sets are regularly updated. It can also handle repetition of both single and multi‐symbol sub‐expressions.

Recently, energy expenditures of the Internet have increased dramatically, raising energy issue of routers an urgent problem in relative research areas. In fact, much device surplus and redundancy are introduced during network planning for rarely appeared traffic peak hours and device failures, wasting energy most of the time. In this work, an energy-aware architecture is proposed for routers, which could trade system performance for energy savings while traffic is low by scaling frequencies of its inner components. We also explore multi-frequency modulation strategies to optimize the energy saving effect. The result shows that our prototype router could save about 40\% of its peak power consumption.

Future Internet requires re-thinking of network infrastructure towards the balance between computing capacities and energy sustainable techniques. As one of computing intensive components, Bloom filters are widely used for network packet processing. In this paper, an energy efficient self-adaptive Bloom filter, EABF, is devoted to a balance of power and performance especially for high performance networks. The basic idea is to give the Bloom Filter the capability to adjust the number of active hash functions according to the current workload automatically. This adaption depends on its control policies. Three policies are presented and compared. We also give the method to implement EABF in hardware for higher performance. It is presented in a two-stage platform based on FPGA where Stage 1 is always active and Stage 2, a secondary stage, is only active when necessary. The platform can also be extended to multi-stages. A control circuit is designed for flexibly changing working stage and reducing both dynamic and static power consumption. Analysis and experiments show that our dynamic two-stage EABF can achieve almost the best power savings as that of the fixed schemes; unlike the fixed schemes that might have much longer latency, EABF maintains nearly 1 clock cycle latency as that of a regular Bloom filter.

Energy saving becomes one of the most important design considerations in wireless cooperative networks which are composed of nodes typically powered by batteries that can supply only a finite amount of energy. In this paper, we propose a dynamic relaying scheme based on relay selection and physical-layer power control with the objective of minimizing the energy consumption for data transmission. We first develop a mathematical model for the cooperative relaying and analyze the total battery energy consumption to forward a symbol. Based on the analytic results and Markov channel model, we formulate the optimization problem that minimizes total average energy consumption as a Markov decision process, with which we can decide an optimal relay and the transmission power distributely. In the proposed scheme, the relay selection process and cooperation mode starts only when the direct transmission between source and destination node failed, which is energy efficient from a network sense. Numerical simulation show that the proposed scheme achieves significant energy savings.

Peer-to-Peer (P2P) mode dominates the way that files are shared over the Internet today. A measurement study on the user behaviour during the P2P file sharing is important and helpful to better understand and design P2P networks. In this study, the authors developed a method to collect information about peers and connections in movie sharing at the BitTorrent client side. Movie is selected as the investigation object since its immense popularity and large size among all the file types over P2P networks. The method proposed in this study can be easily applied to study the distribution behaviour of other types of files. Based on the collected data, the authors have derived 10 observations in three categories: (i) distributions of peers and connections over globe time and local time (after adjustment of time differences); (ii) distributions of peers and connections over geographic areas (at different levels of continents, countries, cities); and (iii) the influence to the above distributions by differences of population, gross domestic product (GDP) and life style.

Deep packet inspection (DPI) has become one of the key components of a Network Intrusion Detection System (NIDS) and it compares packet content to a set of rules written in regular expression. The need to keep up with ever-increasing line speed has forced NIDS designers to move to hardware or high-speed memory where memory resources are limited. In this paper, we present LBM, a novel accelerating scheme for regular expression matching which converts the original byte stream into much shorter integer stream and then matches it with a variant of DFA, called StriD2FA. In the instance of LBM that we realize, 10 to 15 speedup is reasonable while the memory is much smaller than traditional DFA.

Peer-to-Peer (P2P) mode dominates the way that files are shared over the Internet today. A measurement study on the user behavior during the P2P file sharing is important and helpful to better understand and design P2P networks. In this paper, we developed a method to collect information about peers and connections in movie sharing at the BitTorrent client side. Based on the collected data, we have derived 5 observations in the influence upon peers and connections distributions over geographic areas (at different levels of continents, countries, cities) by differences of population, GDP (Gross Domestic Product), time zone and life style.

To cope with the too much energy consumption of base station (BS), this paper firstly gives a green heterogeneous network architecture, in which some BSs could be switched off or set as sleep mode when its local traffic is low, while the resident users rely on the mobile relay network composed by intelligent mobile nodes to connect to one of its neighboring BSs. Moreover, in order to achieve better performance, a mathematical model for relay selection is proposed by considering multiple factors, such as secrecy capacity (SC) for selected channels, remained energy¿iRE¿j for relays and location information. Accordingly, a novel dynamic relay selection approach based on Principal Component Analysis (PCA) is brought forward. Using this approach,the related factors which affect the quality of service (QoS) provisioning most could be found out by processing the observation data, and the their weights could be computed in a real-time way as well. The significant property of this approach is to reduce the useless energy loss by removing the redundant parameters. Finally, simulation results prove that the proposed approach outweights the existing ones in terms of system rewards, average throughput, and network lifetime.

Deep Packet Inspection (DPI) involves searching a packet's header and payload against thousands of rules to detect possible attacks. The increase in Internet usage and growing number of attacks which must be searched for has meant hardware acceleration has become essential in the prevention of DPI becoming a bottleneck to a network if used on an edge or core router. In this paper we present a new multi-pattern matching algorithm which can search for the fixed strings contained within these rules at a guaranteed rate of one character per cycle independent of the number of strings or their length. Our algorithm is based on the Aho-Corasick string matching algorithm with our modifications resulting in a memory reduction of over 98% on the strings tested from the Snort ruleset. This allows the search structures needed for matching thousands of strings to be small enough to fit in the on-chip memory of an FPGA. Combined with a simple architecture for hardware, this leads to high throughput and low power consumption. Our hardware implementation uses multiple string matching engines working in parallel to search through packets. It can achieve a throughput of over 40 Gbps (OC-768) when implemented on a Stratix 3 FPGA and over 10 Gbps (OC-192) when implemented on the lower power Cyclone 3 FPGA.

As line rates increase, the task of designing high performance architectures with reduced power consumption for the processing of router traffic remains important. In this paper, we present a multi-engine packet classification hardware accelerator, which gives increased performance and reduced power consumption. It follows the basic idea of decision-tree based packet classification algorithms, such as HiCuts and HyperCuts, in which the hyperspace represented by the ruleset is recursively divided into smaller subspaces according to some heuristics. Each classification engine consists of a Trie Traverser which is responsible for finding the leaf node corresponding to the incoming packet, and a Leaf Node Searcher that reports the matching rule in the leaf node. The packet classification engine utilizes the possibility of ultra-wide memory word provided by FPGA block RAM to store the decision tree data structure, in an attempt to reduce the number of memory accesses needed for the classification. Since the clock rate of an individual engine cannot catch up to that of the internal memory, multiple classification engines are used to increase the throughput. The implementations in two different FPGAs show that this architecture can reach a searching speed of 169 million packets per second (mpps) with synthesized ACL, FW and IPC rulesets. Further analysis reveals that compared to state of the art TCAM solutions, a power savings of up to 72% and an increase in throughput of up to 27% can be achieved.

Network processors have exploited many aspects of architecture design, such as employing multi-core, multi-threading and hardware accelerator, to support both the ever-increasing line rates and the higher complexity of network applications. Micro-architectural techniques like superscalar, deep pipeline and speculative execution provide an excellent method of improving performance without limiting either the scalability or flexibility, provided that the branch penalty is well controlled. However, it is difficult for traditional branch predictor to keep increasing the accuracy by using larger tables, due to the fewer variations in branch patterns of packet processing. To improve the prediction efficiency, we propose a flow-based prediction mechanism which caches the branch histories of packets with similar header fields, since they normally undergo the same execution path. For packets that cannot find a matching entry in the history table, a fallback gshare predictor is used to provide branch direction. Simulation results show that the our scheme achieves an average hit rate in excess of 97.5% on a selected set of network applications and real-life packet traces, with a similar chip area to the existing branch prediction architectures used in modern microprocessors.

In this paper we present an open source flexible network processor simulation framework called SimNP. Allowing algorithms and applications to be implemented in high level languages such as C or C++, SimNP allows workload characterization, architecture development and performance evaluation. The simulator models several architectural features that are commonly employed by network processors, including multiple processing cores, integrated networking interface and memory controller, and hardware accelerators. Moreover, new features or new modules can also be easily added into this simulator.

Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Internet traffic. With everincreasing ruleset size and line speed, the task of implementing wire speed packet classification with reduced power consumption remains difficult. Software approaches are unable to classify packets at wire speed as line rates reach OC-768, while state of the art hardware approaches such as TCAM still consume large amounts of power.

Caching mechanism has achieved great success in general purpose processor; however, its deployment in Network Processor (NP) raises questions over its effectiveness under the new context. In this study, we thoroughly evaluate the performance of caches in NP with architectural features like multicore, multithread, and integrated packet interface. Our major findings include: (1) In general, a sufficiently large cache effectively reduces the number of memory requests and improves the utilization of the NP computation power. (2) The lower efficiency of private caches caused by duplicate information deteriorates the NP performance under certain circumstances. (3) The appropriate cache block size is constrained by the low spatial locality of network applications. (4) For workloads involving large amount of data movement, increasing cache size cannot bring more benefits when the bottleneck in interconnection bus is reached. In short, caching mechanism in NP can be helpful under appropriate usage.

Packet classification is an important function in a router's line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classification reaching up to OC-192 and even OC-768 with reduced cost and low power consumption remains a challenge. In this paper, the HiCut and HyperCut algorithms are modified making them more energy efficient and better suited for hardware acceleration. The hardware accelerator has been tested on large rulesets containing up to 25,000 rules, classifying up to 77 Million packets per second (Mpps) on a Virtex5SX95T TPGA and 226 Mpps using 65 nm ASIC technology. Simulation results show that our hardware accelerator consumes up to 7,773 times less energy compared with the unmodified algorithms running on a StrongARM SA-1100 processor when classifying packets. Simulation results also indicate ASIC implementation of our hardware accelerator can reach OC- 768 throughput with less power consumption than TCAM solutions.

Packet Classification serves as a plinth for many newly emerging network applications. Most of the previous packet classification schemes are IPv4-oriented, and some of them have achieved high throughput with chip-level parallelism of Ternary Content Addressable Memories (TCAM). However, due to their inefficient utilization of TCAM resources, further upgrade incurs prohibitive hardware costs. As IPv6 will dominate the Next Generation Internet, IPv6-oriented packet classification is of increasing importance. In this paper, we propose a packet classification scheme geared towards IPv6. This scheme incorporates efficient and flexible algorithms for parallelism and distributed storing, which provides an unprecedentedly high throughput with relatively low storage costs. Our scheme also integrates delicate parallel encoding algorithms to maximize the TCAM utilization and increase its throughput. Using commercially available TCAM, the scheme is able to classify 266 million IPv6 packets per second (Mpps), matching 4×OC-768 (160 Gbps) line rate. Key words—Packet Classification, Encoding, IPv6, TCAM

A distribution-graph based scheduling algorithm is proposed together with an extended tree growing technique to deal with the problem of unequal-length block-test scheduling under power dissipation constraints. The extended tree growing technique is used in combination with the classical scheduling approach in order to improve the test concurrency having assigned power dissipation limits. Its goal is to achieve a balanced test power dissipation by employing a least mean square error function. The least mean square error function is a distribution-graph based global priority function. Test scheduling examples and experiments highlight in the end the efficiency of this approach towards a system-level test scheduling algorithm.

A left-edge algorithm approach is proposed in this paper to deal with the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the left-edge algorithm in order to improve the test concurrency under power dissipation limits. Test scheduling examples and experiments are discussed highlighting further research directions toward an efficient system-level test scheduling algorithm.

Classical scheduling approaches are applied here to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. List scheduling-like approaches are proposed first as greedy algorithms to tackle the fore mentioned problem. Then, distribution-graph based approaches are described in order to achieve balanced test concurrency and test power dissipation. An extended tree growing technique is also used in combination with these classical approaches in order to improve the test concurrency having assigned power dissipation limits. A comparison between the results of the test scheduling experiments highlights the advantages and disadvantages of applying different classical scheduling algorithms to the power-constrained test scheduling problem.

The left-edge algorithm is adapted in this paper to deal with the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is used in combination with the left-edge algorithm in order to improve the test concurrency under power dissipation limits. A test scheduling example is discussed highlighting further research directions towards an efficient system-level test scheduling algorithm.