Physical unclonable functions (PUFs) are widely used for hardware security, yet conventional designs often suffer from considerable design overhead, limited placement flexibility, and susceptibility to environmental noise. This work presents DF-PUF, a dual-function, programmable entropy source tailored for secure and resource-efficient ASIC integration. DF-PUF leverages die-level process variations to generate device-unique responses for authentication, while its hardware resources can be dynamically repurposed as memory elements for local data storage when not operating as a PUF, thereby enhancing area efficiency. The architecture supports flexible deployment across the chip layout, facilitating integration in diverse design scenarios. Additionally, DF-PUF incorporates a noise-resilient response conditioning mechanism that mitigates environmental fluctuations, ensuring that output characteristics are predominantly determined by intrinsic process variations. These capabilities are achieved with minimal overhead, making DF-PUF a practical and scalable solution for secure embedded systems. Comprehensive evaluation through circuit-level simulations and silicon measurements on 65nm CMOS test chips demonstrates the proposed design’s superior uniqueness, randomness, and robustness.

This paper presents fusion intelligence (FI), a bio-inspired paradigm that synergistically integrates the intrinsic capabilities of intelligent biological organisms with the advanced potential of artificial intelligence (AI) driven systems. FI harnesses the unique intelligence, sensing, actuation, and mobility attributes of living organisms, such as honeybees, blending these with the sophisticated data-driven problem-solving functionalities of AI. By bridging the gap between natural intelligence (NI) and AI, FI can transform how humans interact with and harness the capabilities of both natural and artificial systems. The paper presents the model of FI and its application to solve practical problems, discusses the challenges and future directions of FI research, emphasizing a generalized approach to solve complex problems, where AI can observe/control NI in a closed-loop system. We demonstrate the potential for FI to enhance the performance of an agricultural IoT system via a simulated case study, which achieves 50% improvement in the efficacy of insect pollination (entomophily).

This paper introduces multi-bit memory-based PUF (MBM PUF), a new PUF architecture designed to enhance the resilience of SRAM PUFs in ASIC applications. The MBM PUF utilizes an SRAM cell as its main component, capitalizing on its simplicity while mitigating weaknesses such as susceptibility to environmental noise and various attacks. As an example, a MBM PUF was implemented within an edge-triggered D flip-flop, a key component in the scan chain used by digital and mixed-signal designs, to achieve enhanced security with minimal area overhead. The concept can also be integrated into other circuits with built-in positive feedback loops, effectively leveraging their resources while minimizing die area. Simulation results in 45 nm CMOS technology show that the proposed security solution can readily fulfill the required performance criteria for a PUF.

The radio spectrum in the sub-6 GHz (FR1) band is crowded and contested, and is sought after by commercial, scientific and defense users. Situational awareness through spectrum sensing, and AI/ML-enabled perception that recognizes behaviors, patterns, modulations, devices and waveforms is a crucial need for emerging autonomous/cognitive radio systems. This work describes measurable progress in the use of extremely low complexity approximate DFT algorithms as multi-beam beamformers in the digital domain for multibeam spatial RF beamforming. The paper begins with a longterm vision for intelligent spectrum awareness across wide bands and multi-directions with multi-chiplet system in package hardware acceleration of both beamforming, Fourier and AI/ML algorithms, followed by a focus account of specific progress with digital architectures and real-time prototype implementations across the 5.7–5.8 GHz band for 32 RF beams. A real-time temporal frequency resolution of 100 kHz across 100 MHz of baseband bandwidth is achieved, across 32 simultaneous fully-digital RF-beams, using a Xilinx Sx475 FPGA implementation. Details of multiplierless approximate DFT beamformers, automated modulation recognition algorithms using AI/ML, analog channelization, spectrum sensing and perception architectures are also discussed. Over-the-air experiments using the RadioML.2018.a dataset confirmed both single source accuracy (better than 97%) and impact of multi-beams on AI/ML performance for multiple strong RFI sources.

This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89K. The chip was fabricated in a 180nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77K, indicate that the channel outputs have high linearity (INL$\mu $s and a detector capacitance of 150pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.

This paper describes a programmable single-chip feedback ASIC for a network of coupled microelectromechanical systems (MEMS) referenced oscillators in the 0.4-15 MHz range. The chip contains differential low-noise amplifiers (LNAs), variable-gain amplifiers (VGAs) and programmable-gain amplifiers (PGAs) for gain control, second-order active-RC band-pass filters (BPFs) for band selection, all-pass filters (APFs) for phase shifting, an automatic level control (ALC) loop, and output buffers to drive mechanical resonators. The feedback transfer function can be fine-tuned via a three-wire serial peripheral interface (SPI) bus. A compensation path with its own PGAs, programmable attenuator, and APF enables removal of electrical feedthrough within the resonator. The chip has 5 differential input paths with independent gain control, 1–2 of which are used for local feedback (to realize oscillations) while the others accept inputs from other oscillators. The chip has been fabricated in 180 nm CMOS and consumes 4.6 mW at 1.8 V. In initial tests, it is integrated with a 2 MHz quartz resonator$(Q=2000)$to realize an oscillator with low phase noise (-117 dBc/Hz at 1 kHz offset). Additionally, the chip's ability to synchronize oscillators is validated via a 1:1 injection locking experiment.

This paper describes an analog CMOS IC for fast and fully-parallel finite-difference time-domain (FDTD) simulations of 2D electromagnetic (EM) problems. The chip uses discrete-time switched-current (SI) networks to model Maxwell's equations in 2D while minimizing the effects of device mismatch on solver accuracy. A prototype design in 180 nm technology implements a$16\times 16$solver grid within an active area of 44.5 mm2while consuming 345 mW at a clock frequency of 20 MHz.

This paper describes an adaptive noise generator circuit suitable for on-chip simulations of stochastic chemical kinetics. The circuit uses amplified BJT white noise and adaptive low-pass filtering to emulate the power spectrum and autocorrelation of random telegraph signals (RTS) with Poisson-distributed level transitions. A current-mode implementation in the AMS 0.35$\mu \text{m}$BiCMOS process shows excellent agreement with theoretical results from the Gillespie stochastic simulation algorithm over a 60 dB range in mean current levels (modeling molecule count numbers). The circuit has an estimated layout area of 0.032 mm2 and typically consumes 400$\mu \text{A}$, which are 73% and 50% less, respectively, than prior implementations. Moreover, it does not require any off-chip capacitors. Experimental results from a discrete board-level implementation of the circuit are in good agreement with theoretical predictions.

This paper describes a highly-efficient and compact GaNFET-based power amplifier for use in miniaturized low-field nuclear magnetic resonance (NMR) spectrometers and magnetic resonance imaging (MRI) scanners based on CMOS application-specific integrated circuit (ASICs). The amplifier utilizes a H-bridge topology with bootstrap driver and can work at frequencies up to several MHz. It also includes a GaNFET-based Q-switch to damp the coil after each RF pulse. Tests with a tuned probe at 2 MHz show > 90% efficiency while delivering ~350 W of power to the coil, and a ring-down time of ~4 μs.

This paper describes a circuit theoretic formulation for simulating the Schrödinger equation using classical analog circuits. Update equations for a finite difference time domain (FDTD) Schrödinger equation solver with absorbing boundary conditions (ABCs) are used to derive signal flow graphs that naturally map to switched capacitor (SC) circuits. A prototype implementation of a fully-parallel SC FDTD solver with 128 spatial points and a clock frequency of 2 MHz is analyzed and simulated using a standard 180 nm CMOS process.

A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update equations are realized using analog circuits which compute continuous-time solutions of the PDE with prescribed initial and boundary conditions. The proposed concept is demonstrated in simulation via an integrated circuit (IC) design of a nonlinear acoustic wave equation solver in 180 nm CMOS technology. Analog arithmetic operations (multiply, scale, and add) are realized in parallel using fully differential op-amps and analog multipliers. The proposed IC computes the PDE solution in parallel at 33 discrete spatial points and has a simulated bandwidth and power consumption of approximately 2 MHz and 3 W, respectively. The performance of the IC is simulated using foundry-supplied device models and quantified using i) the mean squared difference between the circuit simulation results and FDTD simulations, and ii) the noise to signal energy ratio. Acceptable accuracy is obtained, with error metric values varying between -7 and -30 dB for various configurations of the problem. Comparison of the custom analog IC simulations with MATLAB- and C-based FDTD code running on a modern workstation shows an expected average speedup of 205× and 140×, respectively.

This paper describes a single-chip analog computer for solving the one dimensional (1-D) wave equation. The chip integrates a 16-point discrete-time but continuous-valued finite-difference solver with spatially-programmable wave velocity, selectable boundary conditions, and arbitrary input excitation waveforms. Built-in Δ-Σ analog-to-digital converters (ADCs) allow the solution results to be easily read out by a digital processor. The design was realized in TSMC 180 nm CMOS and has an active area of 2.81 mm × 2.64 mm. Experimental results prove the functionality of the proposed analog solver.

A multi-port spatio-temporal noise-shaping ADC is proposed to process plane waves received by spatially-oversampled antenna arrays. In the proposed multi-port ADC, the desired plane waves are processed with a spatial low-pass frequency response whereas the noise and distortion are shaped with a spatial high-pass frequency response. By employing a first-order Butterworth filter, approximately circular passbands and stopbands are achieved for the signal and the noise transfer functions, respectively. The proposed noise-shaping system is designed in the TSMC 180 nm CMOS process, with ADCs and DACs modeled as noise sources. Circuit simulation results show that the proposed system can achieve a bandwidth of 50 MHz.

This work presents a fully-integrated double-quadrature Weaver receiver for monitoring the NIST time and frequency reference radio station WWV across multiple channels in the 2.5-20 MHz range. The design takes advantage of the Weaver architecture's elimination of image rejection filters. The receiver uses a broadband low-noise amplifier (LNA) with an input-referred noise power spectral density (PSD) of1/2for high sensitivity. Instead of large filters, a double-quadrature down-conversion process is used to remove the image signal. Both local oscillators (LOs) are frequency- and phase-locked to each other via an on-chip frequency divider, and their I and Q components are generated by highly-precise digital phase splitters. The receiver was fabricated in the TSMC 180 nm CMOS process and consumes 24.9 mW. Measurements show in-band gain > 40 dB, noise figure (NF) <; 2.9 dB, and maximum image rejection ratio (IRR) of 29 dB without calibration.

The superior performance of deep learning (DL) has sent shock waves in the machine learning community. The high adoption rate of DL has set new demands on computational throughput, latency, and power efficiency of the computing infrastructure. In addition to conventional approaches to acceleration of the inference component of DL systems based on GPUs, cloud computing, ASIC/FPGAs and custom vector processors (such as tensor processing units), there is renewed interest in high-frequency analog circuits for DL inference. Analog computing is a potential candidate for meeting challenging requirements in throughput, latency and power efficiency. Because DL inference has superior noise resilience and relatively low accuracy needs (typically less than 8 bits), analog circuits can provide a promising alternative to all-digital accelerators. This paper presents early work on the design of an analog CMOS accelerator that performs analog convolution and decision operations in parallel and in real-time by pairing a high-frequency operational amplifier-based CNN filtering kernel with a rectified linear unit (ReLu) non-linearity based on an active precision rectifier circuit. The analog accelerator was designed in a 45 nm CMOS process and simulated in Cadence Spectre. Image convolution results are presented and compared with MATLAB simulations. The proposed solution also employs Xilinx RF System-on-Chip (SoC) devices based on the Xilinx ZCU1285 RFSoC platform to interface digital inputs and outputs with the proposed RF-rate analog inference accelerator.

In this paper, we propose solutions to Maxwell's equations that can be computed using analog computers. Spatially-discrete time-continuous (SDTC) algorithms running on analog computers can be potentially faster and more energy-efficient than fully-discrete numerical solvers. The implementations of fully-discrete partial differential equation (PDE) solvers on high speed digital processors, such as graphics processing units (GPUs), take many clock cycles to compute a single temporal frame of the update equation and thus have relatively low equivalent bandwidths. Our approach is to directly implement temporal recursions in continuous-time by using analog circuits. Such circuits can have bandwidths that greatly exceed the equivalent bandwidths of GPUs. In particular, we propose two analog computing methods that compute the SDTC solutions to Maxwell's equations. In addition to Maxwell's equations, such platforms can be used to accelerate other hard computational problems that involve PDEs derived from continuous-time systems. In continuous-time in Laplace domain (CTLD) method (first approach), the spatial domain partial derivatives in the governing PDE are approximated using discrete finite differences, while applying the Laplace transformation along the time dimension. The resulting spatially-discrete time-continuous update equation is utilized to design an analog circuit that can compute the continuous-time solution. The all-pass delay approximate (APDA) method (second approach) replaces the discrete-time difference operators in the standard finite difference time domain (FDTD) cell (Yee cell) using continuous-time delay operators, which can be realized using analog all-pass filters. Both methods have been simulated using ideal analog circuits in Cadence Spectre for the Dirichlet, Neumann, and radiation boundary conditions. The performance of the proposed methods have been quantified using i) mean squared differences between the results and fully-discrete FDTD simulations, and ii) the noise to signal energy ratio. The CTLD and APDA methods are able to compute the solutions to Maxwell's equations with a noise energy to signal energy ratio γ better than -26 dB and -19 dB, respectively. Both methods have been extended to design analog circuits that compute the continuous-time solution of the 1-D and 2-D wave equations. The CTLD-based 1-D and 2-D analog wave equation solvers are able to compute the solutions with γ better than -72 dB and -60 dB, respectively. The APDA-based 1-D wave equation solver is simulated with a dominant-pole model (which better approximates the non-ideal circuit behavior) along with a propagation delay compensation technique. The non-ideal analog models compute the solution with a difference smaller than -13 dB (in terms of γ). Experimental results from a simplified board-level low-frequency implementation are also presented. The key challenges toward CMOS implementations of the proposed solvers are identified and briefly discussed with possible solutions.

In order to improve food quality and safety, accurate and cost-efficient quality assurance (QA) methods are of great importance. One type of food that can benefit from new quality assurance methods are cheese products. This paper describes the use of low-cost hand-held or benchtop sensors based on low-field (≤ 0.5 T) nuclear magnetic resonance (NMR) for quantification fat, water, and sodium content, which are three commonly-used QA metrics of cheese. The proposed methods are expected to be useful for QA of cheese as well as other dairy products in production and retail applications. Experimental measurements of water and fat percentages as well as sodium quantity on a set of cheese samples confirm that the values of NMR-based food composition metrics are in excellent agreement with those derived from the product label.

This paper proposes an architecture that reduces the complexity of traditional N-bit ADCs used in focal plane array (FPA) dish receivers by replacing them with multiport ADCs. The proposed ADC architecture uses a multi-dimensional (MD) noise-shaping method based on a Δ-Σ architecture for wideband RF signals that are received on the focal region of a parabolic dish/lens antenna. In the M-port noise shaping technique, the N-bit quantizers of conventional ADCs are replaced by 1-bit quantizers followed by a spatial feedback system based on a Δ-Σ architecture with spatial oversampling, which shapes the quantization noise out of the region of support (ROS) of the electromagnetic (EM) waves received from the dish. The paper discusses the case of a prime-axis pencil beam in detail for the simplified case of a linear FPA. Simulations for 2.1-5.1 GHz wideband dish signals show 16-element FPAs with oversampling ×l, ×2, and ×4 shows ADC effective number of bits (ENoB) improvements of 2.5 bits, 3.2 bits and 4.2 bits, respectively. Extensions to off-axis pencil-beams and rectangular FPAs will be considered in future work. Potential applications exist across microwave and mm-wave bands, for radio astronomy, radar, and wireless communications.

We describe a current-mode multi-beam beamforming approach for 5G wireless applications based on a low-complexity approximate-DFT (a-DFT). Dynamic current mirrors are used to cancel errors in the current copying and scaling operations required to realize a-DFT matrices, thus resulting in an accurate and scalable architecture. The circuit design for the case of 8-point a-DFT has been validated with transistor-level simulations in the UMC 0.18 μm CMOS process.

We describe a switched-gain control (SGC) technique for improving the settling time and peak overshoot of phase-locked loops (PLLs). We improve upon previous work by designing the controller to work with time-varying inputs, such as linear phase ramps in PLLs. We then develop circuits to implement the resulting control laws. Our results are supported by transistor-level simulations in a 0.18μm CMOS process.

This paper presents a 1.3mA current stimulator integrated circuit (IC) with closed-loop, active charge balancing for nerve interfacing applications. The stimulator employs two current-based digital-to-analog converters (DACs), one each for anodic and cathodic phases, with binary-weighted transistors and 2b-programmable least-significant bit (LSB) currents. The biphasic, cathodic-leading, stimulus current pulse amplitude is 5b-programmable in four ranges of ~ 12-341μA, 23-682μA, 32-992μA, and 42-1,300μA. A low-power (~10μW), active charge balancer monitors the site voltage after each stimulus cycle and, if necessary, injects positive or negative current pulses via two 3b auxiliary DACs to bring the site voltage back within a userset safety window. All digital circuitry operate from 3.3V, whereas the stimulator output stage operates from 5V with a stimulus site common-mode voltage of 3.3V for better use of the available voltage headroom in cathodic-leading, single-supply stimulation. A prototype chip is fabricated in 0.5μm 2P/3M CMOS, and measured results from benchtop electrical characterization of the chip are presented.

This paper presents an integrated low-power analog front end (AFE) for simultaneously detecting electrocardiogram (ECG) and respiration rate (RR). A low-power low-noise preamplifier is designed to amplify both the ECG and RR signals. A current-driven passive mixer is used in the RR path to up-convert the RR signal so that the ECG signal can be filtered out. The modulated RR signal is then down-converted to baseband to be further amplified and detected. Quadrature (I and Q) drive signals for the mixers are generated on-chip from an external 20 kHz clock signal. The receiver is fabricated on the OnSemi 0.5 μm CMOS process. Both simulation and preliminary measurement results verify the functionality of this work. The overall gain for the ECG and RR signals are 40 dB and 70 dB respectively, and the circuit draws 6.2 μA from a 3 V power supply. To the best of the authors' knowledge, this is the first work in the literature that shows integrated RR and ECG signal detection with such low power consumption.

We present an ultra-low-power broadband wakeup RF receiver (WUR) for autonomous wireless sensor nodes (WSNs). Decreasing static power consumption of the WUR is critical for increasing the operational lifetime of the node. Several techniques are introduced to minimize power consumption while maintainin sensitivity, including step-up impedance transformation, an ultra-low-power RF amplifier, and digital offset adjustment. RF energy harvesting using a rectifier is also proposed to increase node lifetime. The receiver is designed and simulated using UMC 65 nm CMOS and has a power consumption of 11.5 nW. It successfully demodulates 1 kbps on-off-keyed data from a -60 dBm carrier at 50 MHz with an impedance of 1.8 kΩ across the input terminals of the RF receiver. This work surpasses state-of-the-art WURs in terms of sensitivity-power trade-off.

The production and sale of counterfeit and substandard pharmaceutical products, such as essential medicines, is an important global public health problem. We describe a chemometric passport-based approach to improve the security of the pharmaceutical supply chain. Our method is based on applying nuclear quadrupole resonance (NQR) spectroscopy to authenticate the contents of medicine packets. NQR is a non-invasive, non-destructive, and quantitative radio frequency (RF) spectroscopic technique. It is sensitive to subtle features of the solid-state chemical environment and thus generates unique chemical fingerprints that are intrinsically difficult to replicate. We describe several advanced NQR techniques, including two-dimensional measurements, polarization enhancement, and spin density imaging, that further improve the security of our authentication approach. We also present experimental results that confirm the specificity and sensitivity of NQR and its ability to detect counterfeit medicines.

We describe a novel wireless receiver architecture that is a broadband generalization of narrowband heterodyning systems commonly used in radio. It can be constructed with cochlea-like traveling-wave structures. We show how this architecture exploits the efficiency of cochlear spectrum analysis to perform parallel, multi-scale analysis of wideband signals. We discuss analogies between spectrum analysis in our architecture and the process of successive-subranging analog-to-digital conversion. When combined with our prior work on an RF cochlea, such architectures may be useful in cognitive radios for creating “RF foveas” that select the narrowband components present within wideband, but spectrally sparse signals.

We analyze and present an input gain-varying scheme for maximizing dynamic range in a well-known Gm-C bandpass filter by both minimizing noise for small input signals, and by achieving balanced swing levels at all filter nodes for large input signals. A micropower bandpass filter suitable for use in cochlear implants and other power-constrained biomedical applications was implemented and tested in subthreshold CMOS. At a center frequency of 1.4 kHz and quality factor of 4, the filter has 70 dB of dynamic range (57 dB maximum SNR, 2.5% total harmonic distortion (THD)) and consumes 2.55 muW of power.

We exploit the detailed similarities between electronics and chemistry to develop efficient, scalable bipolar or subthreshold log-domain circuits that are dynamically equivalent to networks of chemical reactions. Our circuits can be used for transient and steady-state simulations, parameter estimations and sensitivity analyses of large-scale biochemical networks. They allow the topology, rate constants, inputs, outputs and initial conditions of the reaction network to be programmed. When reactants are present in low concentrations, random fluctuations in reaction rates become significant; we can also model such stochastic effects. We present experimental results from a proof-of-concept chip implemented in 0.18 mum CMOS technology.

This paper presents work on ultra-low-power circuits for brain-machine interfaces with applications for paralysis prosthetics, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; radio-frequency (RF) impedance modulation for low-power data telemetry; a wireless link for efficient power transfer; mixed-signal system integration for efficiency, robustness, and programmability; and circuits for wireless stimulation of neurons. Experimental results from chips that have recorded from and stimulated neurons in the zebra-finch brain and from RF power-link systems are presented. Circuit simulations that have successfully processed prerecorded data from a monkey brain and from an RF data telemetry system are also presented.

This paper introduces a positive-feedback self-biasing technique for operational amplifiers (op-amps) which enables their power consumption to adapt to their environment: The power consumption of one of our op-amps scales almost linearly with load capacitance, input signal frequency, and output signal swing. Our op-amp is primarily intended for low power switched-capacitor applications. A voltage follower built in the MOSIS/AMI 0.5/spl mu/m process with our op-amp has a measured power consumption that varies between 1.38/spl mu/W and 90/spl mu/W, as the load capacitance varies from 1pF to 100pF.

We describe an approximately-PTAT CMOS current reference circuit that is useful for large analog systems. An innovative capacitively-coupled startup circuit that draws no static power is also presented. Experimental results from 0.5 mum and 0.18 mum implementations are shown. Both references are cascoded and use no resistors. The 0.18 mum version operates down to VDD= 0.5V

We develop a technique for approximating a WKB-type solution to a wave equation as a cascade of unidirectional filters. This allows us to design improved building-block circuits for a bio-inspired RF cochlea. By comparing properties of different cochlear filter stages using experimental results and circuit simulations, we demonstrate that our technique significantly improves the characteristics of the RF cochlea